Keyword : low power


Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers
Kenya KONDO Koichi TANNO Hiroki TAMURA Shigetoshi NAKATAKE 
Publication:   
Publication Date: 2018/05/01
Vol. E101-A  No. 5 ; pp. 748-754
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
voltage referencebandgap referencecurrent modeOPAMP lesslow voltagelow powersubthreshold
 Summary | Full Text:PDF(1.4MB)

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation
Toshinori HOSOKAWA Atsushi HIRAI Yukari YAMAUCHI Masayuki ARAI 
Publication:   
Publication Date: 2017/09/01
Vol. E100-D  No. 9 ; pp. 2118-2125
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
low powertest generationcapture safe test vectorstest vector synthesisunsafe faults
 Summary | Full Text:PDF(1.4MB)

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier
Teruki SOMEYA Hiroshi FUKETA Kenichi MATSUNAGA Hiroki MORIMURA Takayasu SAKURAI Makoto TAKAMIYA 
Publication:   
Publication Date: 2017/04/01
Vol. E100-C  No. 4 ; pp. 349-358
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
voltage detectorvoltage referencelow powerlow voltagemultiple voltage copier
 Summary | Full Text:PDF(1.6MB)

A Low Power Buffer-Feedback Oscillator with Current Reused Structure
Chang-Wan KIM Dat NGUYEN Jong-Phil HONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/12/01
Vol. E99-C  No. 12 ; pp. 1335-1338
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
millimeter-wavelow powerbuffer-feedbackoscillator
 Summary | Full Text:PDF(402.5KB)

Improvement of Data Utilization Efficiency for Cache Memory by Compressing Frequent Bit Sequences
Ryotaro KOBAYASHI Ikumi KANEKO Hajime SHIMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8 ; pp. 936-946
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
cache memorylow powerfrequent bit sequences
 Summary | Full Text:PDF(799.9KB)

A Low Power Pulse Generator for Test Platform Applications
Jen-Chieh LIU Pei-Ying LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1415-1416
Type of Manuscript:  Special Section LETTER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
arbitrary waveformpulse generatorlow power
 Summary | Full Text:PDF(569KB)

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications
Nobutaro SHIBATA Yoshinori GOTOH Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 717-726
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
10T typebitline capacitanceCMOSgate arrayhigh speedlow powermemory-oriented base cellshared contacttwo-port SRAM
 Summary | Full Text:PDF(1.7MB)

Pseudo-CMOS with Re-Pull-Down Transistor: A Low Power Inverter Design for Thin-Film Transistors
Lihao ZHONG Ruohe YAO Fei LUO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 727-729
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
Pseudo-CMOSlow powerre-pull-downthin-film transistor
 Summary | Full Text:PDF(374.7KB)

Low-Power Driving Technique for 1-Pixel Display Using an External Capacitor
Hiroyuki MANABE Munekazu DATE Hideaki TAKADA Hiroshi INAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/11/01
Vol. E98-C  No. 11 ; pp. 1015-1022
Type of Manuscript:  INVITED PAPER (Special Section on Electronic Displays)
Category: 
Keyword: 
LCDPDLC1-pixellow powercapacitor
 Summary | Full Text:PDF(1.2MB)

A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications
Chia-Wen CHANG Yuan-Hua CHU Shyh-Jye JOU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/08/01
Vol. E98-C  No. 8 ; pp. 882-891
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
all-digital phase-locked loophierarchical digitally controlled oscillatorslow voltagelow powerfast lock-inlow jitter
 Summary | Full Text:PDF(3.6MB)

A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit
Teerachot SIRIBURANON Wei DENG Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/06/01
Vol. E98-C  No. 6 ; pp. 471-479
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
low powerlow phase noiseclass-C VCOstart-upCMOSreplica-bias circuit
 Summary | Full Text:PDF(1.5MB)

A Low Power and Hardware Efficient Syndrome Key Equation Solver Architecture and Its Folding with Pipelining
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/05/01
Vol. E98-A  No. 5 ; pp. 1058-1066
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Reed-Solomon codesyndrome key equation solutionlow powerfolding
 Summary | Full Text:PDF(893KB)

Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD
Bing XU Shouyi YIN Leibo LIU Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/02/01
Vol. E98-D  No. 2 ; pp. 243-251
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Architecture
Keyword: 
loop mappingsoftware pipeliningDual-VDDlow powerGraph Minor
 Summary | Full Text:PDF(1.7MB)

Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults
Yukihiro SASAGAWA Jun YAO Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2014/12/01
Vol. E97-D  No. 12 ; pp. 3083-3091
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Architecture
Keyword: 
adaptive redundancysetup error recoveryDVSlow powerAVFILP
 Summary | Full Text:PDF(2.4MB)

A Low Power 2×28Gb/s Electroabsorption Modulator Driver Array with On-Chip Duobinary Encoding
Renato VAERNEWYCK Xin YIN Jochen VERBRUGGHE Guy TORFS Xing-Zhi QIU Efstratios KEHAYAS Johan BAUWELINCK 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2014/08/01
Vol. E97-B  No. 8 ; pp. 1623-1629
Type of Manuscript:  Special Section PAPER (Special Section on EU's FP7 ICT R&D Project Activities on Future Broadband Access Technologies in Conjunction with Main Topics of 2013 IEICE ICT Forum)
Category: 
Keyword: 
56Gb/sEAM driverlow powerarrayBiCMOSoptical duobinary coding
 Summary | Full Text:PDF(4.1MB)

An Energy-Efficient ΔΣ Modulator Using Dynamic-Common-Source Integrators
Ryo MATSUSHIBA Hiroaki KOTANI Takao WAHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/05/01
Vol. E97-C  No. 5 ; pp. 438-443
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
ΔΣ modulatordata converterlow poweranalog circuitdynamic circuit
 Summary | Full Text:PDF(1.2MB)

Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC
Jeong-Gun LEE Myeong-Hoon OH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 253-263
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuitFPGA deviceMIPS processorlow power
 Summary | Full Text:PDF(1.7MB)

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters
Takashi MIYAMORI Hui XU Hiroyuki USUI Soichiro HOSODA Toru SANO Kazumasa YAMAMOTO Takeshi KODAKA Nobuhiro NONOGAKI Nau OZAKI Jun TANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 360-368
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
many-corenetwork-on-chipVLIWlow powerface detectionH.264super resolution
 Summary | Full Text:PDF(4.2MB)

Parallel Cyclostationarity-Exploiting Algorithm for Energy-Efficient Spectrum Sensing
Arthur D.D. LIMA Carlos A. BARROS Luiz Felipe Q. SILVEIRA Samuel XAVIER-DE-SOUZA Carlos A. VALDERRAMA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2014/02/01
Vol. E97-B  No. 2 ; pp. 326-333
Type of Manuscript:  Special Section PAPER (Special Section on Technologies for Effective Utilization of Spectrum White Space)
Category: 
Keyword: 
cognitive radiocyclostationaritylow powerparallel scalabilityspectrum sensing
 Summary | Full Text:PDF(938.3KB)

Low-Power Dynamic MIMO Detection for a 4×4 MIMO-OFDM Receiver
Nozomi MIYAZAKI Shingo YOSHIZAWA Yoshikazu MIYANAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/01/01
Vol. E97-A  No. 1 ; pp. 306-312
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
wireless communicationsMIMO detectionlow powerDVFS
 Summary | Full Text:PDF(1.7MB)

Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs
Hao ZHANG Hiroki MATSUTANI Yasuhiro TAKE Tadahiro KURODA Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/12/01
Vol. E96-D  No. 12 ; pp. 2753-2764
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
3-D network on chip (3-D NoC)wirelessinductive-couplinglow poweron/off vertical link
 Summary | Full Text:PDF(2MB)

Region-Based Way-Partitioning on L1 Data Cache for Low Power
Zhong ZHENG Zhiying WANG Li SHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/11/01
Vol. E96-D  No. 11 ; pp. 2466-2469
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
cachelow powerregion-basedway-partitioning
 Summary | Full Text:PDF(506.9KB)

Low Power Design of Asynchronous Datapath for LDPC Decoder
XiaoBo JIANG DeSheng YE HongYuan LI WenTao WU XiangMin XU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/09/01
Vol. E96-A  No. 9 ; pp. 1857-1863
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LDPC codeasynchronous designlow poweraddercomparatorcomparator-MUX
 Summary | Full Text:PDF(2.2MB)

Data Convertors Design for Optimization of the DDPL Family
Song JIA Li LIU Xiayu LI Fengfeng WU Yuan WANG Ganggang ZHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/09/01
Vol. E96-C  No. 9 ; pp. 1195-1200
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
convertordifferential power analysis (DPA)information securitydelay-based dual-rail precharge logic (DDPL)low power
 Summary | Full Text:PDF(1.3MB)

Scan-Out Power Reduction for Logic BIST
Senling WANG Yasuo SATO Seiji KAJIHARA Kohei MIYASE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 2012-2020
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
low powerBISTmulti-cycle testshift power
 Summary | Full Text:PDF(2.2MB)

A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application
Hisashi IWAMOTO Yuji YANO Yasuto KURODA Koji YAMAMOTO Kazunari INOUE Ikuo OKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/08/01
Vol. E96-C  No. 8 ; pp. 1076-1082
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
routeraddress lookuppower consumptionsearch engineTCAMlow power
 Summary | Full Text:PDF(2.8MB)

Selective Check of Data-Path for Effective Fault Tolerance
Tanvir AHMED Jun YAO Yuko HARA-AZUMI Shigeru YAMASHITA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/08/01
Vol. E96-D  No. 8 ; pp. 1592-1601
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
low powerfault-tolerant computingFU array
 Summary | Full Text:PDF(903.6KB)

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC
Muchen LI Jinjia ZHOU Dajiang ZHOU Xiao PENG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6 ; pp. 1366-1375
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
HEVCH.264/AVCdeblocking filterdual-modelow powerSHVHD
 Summary | Full Text:PDF(2.7MB)

A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer
Teerachot SIRIBURANON Takahiro SATO Ahmed MUSA Wei DENG Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/06/01
Vol. E96-C  No. 6 ; pp. 804-812
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
low phase noiselow powertail-current modulationimpulse sensitivity functionsuper-harmonic coupled QVCOpush-push VCO
 Summary | Full Text:PDF(2.2MB)

Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors
Kazuhito ITO Takuya NUMATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 463-472
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low powerfunctional unitnarrow operand
 Summary | Full Text:PDF(1.6MB)

A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method
Hyuk-Jun LEE Seung-Chul KIM Eui-Young CHUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/04/01
Vol. E96-D  No. 4 ; pp. 963-966
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
routerpacket memorylow powerTCP
 Summary | Full Text:PDF(252.1KB)

A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor Networks
Mitsuo NAKAMURA Mamoru UGAJIN Mitsuru HARADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/01/01
Vol. E96-C  No. 1 ; pp. 93-101
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
intra-symbol intermittentRF front endlow powerwireless receiverRF CMOSsensor network
 Summary | Full Text:PDF(2.7MB)

Region Oriented Routing FPGA Architecture for Dynamic Power Gating
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2199-2207
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
FPGAlow powerswitch boxrouting
 Summary | Full Text:PDF(4.3MB)

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System
Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2208-2219
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
dual-vddmin-cutvoltage assignmentlow powertiming constraints
 Summary | Full Text:PDF(1.5MB)

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path
Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2319-2329
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
adaptive redundancysetup error recoveryDVSlow powerAVF
 Summary | Full Text:PDF(4.1MB)

A Novel 400-Gb/s (100-Gb/s4) Physical-Layer Architecture Using Low-Power Technology
Masashi KONO Akihiro KANBE Hidehiro TOYODA Shinji NISHIMURA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2012/11/01
Vol. E95-B  No. 11 ; pp. 3437-3444
Type of Manuscript:  PAPER
Category: Transmission Systems and Transmission Equipment for Communications
Keyword: 
Ethernetlow powerphysical layersingle-wavelength transmission
 Summary | Full Text:PDF(5.6MB)

Low Power Clock Gating for Shift Register
Ki-Sung SOHN Da-In HAN Ki-Ju BAEK Nam-Soo KIM Yeong-Seuk KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/08/01
Vol. E95-C  No. 8 ; pp. 1447-1448
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
low powersmall areaclock gating circuit
 Summary | Full Text:PDF(209.2KB)

A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF)
Xiayu LI Song JIA Limin LIU Yuan WANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/06/01
Vol. E95-C  No. 6 ; pp. 1125-1127
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
flip-floppulse generator freehigh speedlow power
 Summary | Full Text:PDF(255.4KB)

Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating
Shuta TOGASHI Takashi OHSAWA Tetsuo ENDOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5 ; pp. 854-859
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
MTJnonvolatilefine-grained power gatingcounter unitlow power
 Summary | Full Text:PDF(1.6MB)

Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs)
Gibong LEE Woo Young CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5 ; pp. 910-913
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
low powerpropagation delayenergy dissipationtunneling field-effect transistor (TFET)
 Summary | Full Text:PDF(518.8KB)

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring
Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 487-494
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
pressure sensingurinary bladderSoClow powerASIP
 Summary | Full Text:PDF(1.3MB)

A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes
Kazuhito ITO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/04/01
Vol. E95-A  No. 4 ; pp. 767-775
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
Viterbi decoderconvolutional codetrace backsurvivor memorylow power
 Summary | Full Text:PDF(1.5MB)

An Energy-Efficient Full Adder Cell Using CNFET Technology
Mohammad Reza RESHADINEZHAD Mohammad Hossein MOAIYERI Kaivan NAVI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 744-751
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
CNFETFull adderHigh performancelow powernanotechnology
 Summary | Full Text:PDF(1.2MB)

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 314-323
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology
Keyword: 
FPGAlow powerregionhierarchical designpower consumption
 Summary | Full Text:PDF(570.9KB)

CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes
Hong-Yi HUANG Shiun-Dian JAN Yang CHOU Cheng-Yu CHEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/02/01
Vol. E95-C  No. 2 ; pp. 275-283
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
differential logiccharge redistributionlow powerhigh speedmultiplier-accumulator
 Summary | Full Text:PDF(775KB)

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture
Ce LI Yiping DONG Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2519-2527
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
FPGAlow powerpower domainpower consumption
 Summary | Full Text:PDF(7.7MB)

A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling
Byung-Do YANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2676-2684
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
charge-recyclingDC-DC conversionlow poweron-chip
 Summary | Full Text:PDF(1.4MB)

A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio
Toshihiro KONISHI Shintaro IZUMI Koh TSURUDA Hyeokjong LEE Takashi TAKEUCHI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11 ; pp. 2287-2294
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Mobile Information Network and Personal Communications
Keyword: 
MRSSmulti-resolution spectrum sensingcognitive radiowireless sensor networklow power
 Summary | Full Text:PDF(1.8MB)

An Adaptive Various-Width Data Cache for Low Power Design
Jiongyao YE Yu WAN Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/08/01
Vol. E94-D  No. 8 ; pp. 1539-1546
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
low powerdata cachefrequent valuesnarrow-width values
 Summary | Full Text:PDF(759.8KB)

A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques
Byeong-Woo KOO Seung-Jae PARK Gil-Cho AHN Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/08/01
Vol. E94-C  No. 8 ; pp. 1282-1288
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCpipelinelow powerSHA-freecircuit sharingtwo-step reference selection
 Summary | Full Text:PDF(2.1MB)

Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism
Jiongyao YE Yingtao HU Hongfeng DING Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/07/01
Vol. E94-D  No. 7 ; pp. 1398-1408
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
low powerinstruction cacheinstruction fetch mechanism
 Summary | Full Text:PDF(951.6KB)

A 1-Mbps 1.6-µA Active-RFID CMOS LSI for the 300-MHz Frequency Band with an All-Digital RF Transmitting Scheme
Kenji SUZUKI Mamoru UGAJIN Mitsuru HARADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 1084-1090
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
active tagsRFIDVHFlow powertransmitterOOKwireless sensor networks
 Summary | Full Text:PDF(1.8MB)

Low Power Platform for Embedded Processor LSIs
Toru SHIMIZU Kazutami ARIMOTO Osamu NISHII Sugako OTANI Hiroyuki KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 394-400
Type of Manuscript:  INVITED PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
low powerprocessoroperating systemdistributed processing
 Summary | Full Text:PDF(1.2MB)

Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining
Tianruo ZHANG Chen LIU Minghui WANG Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 401-410
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
H.264 encodingVLSI architectureregion-of-interestlow power
 Summary | Full Text:PDF(3.3MB)

Low Power Bus Binding Exploiting Optimal Substructure
Ji-Hyung KIM Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/01/01
Vol. E94-A  No. 1 ; pp. 332-341
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerbus bindingswitching activitytable decompositionoptimal substructure
 Summary | Full Text:PDF(881.2KB)

A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS
Yanfei CHEN Sanroku TSUKAMOTO Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2600-2608
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
ADCsuccessive approximationcharge redistributioncalibrationlow power
 Summary | Full Text:PDF(1.4MB)

Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
Xin MAN Takashi HORIYAMA Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2472-2480
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
automatic clock gating generationlow powerdynamic power reductionBDD
 Summary | Full Text:PDF(1.3MB)

Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems
Tetsuo YOKOYAMA Gang ZENG Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/10/01
Vol. E93-D  No. 10 ; pp. 2737-2746
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
battery-aware voltage schedulingdynamic voltage scalinglow powerreal-time systems
 Summary | Full Text:PDF(666.6KB)

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment
Benjamin STEFAN DEVLIN Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7 ; pp. 1319-1328
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self synchronousfpgapipeline alignmentlow powerhigh throughputdynamic logicdual pipeline
 Summary | Full Text:PDF(6.3MB)

An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder
Sung-Jin KIM Minchang CHO SeongHwan CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6 ; pp. 785-795
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
EPCglobalClass 1Generation 2RFIDRFID tagpulse interval encodedpassivelow powerPIE decodercalibration
 Summary | Full Text:PDF(7.1MB)

A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
Lechang LIU Zhiwei ZHOU Takayasu SAKURAI Makoto TAKAMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6 ; pp. 796-802
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
impulse radio ultra-wideband (IR-UWB)charge-domain sampling correlatorscharge injectionvariable threshold comparatorlow power
 Summary | Full Text:PDF(1.4MB)

A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications
Katsumi DOSAKA Daisuke OGAWA Takahito KUSUMOTO Masayuki MIYAMA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5 ; pp. 685-695
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
TCAMcharge recyclinglow powerlow noiselow operating current
 Summary | Full Text:PDF(4.3MB)

A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits
Jin-Fa LIN Yin-Tsung HWANG Ming-Hwa SHEU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/04/01
Vol. E93-A  No. 4 ; pp. 843-845
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
signal transition detectionpulse generationself-timed circuitlow power
 Summary | Full Text:PDF(215.3KB)

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints
Hsi-An CHIEN Cheng-Chiang LIN Hsin-Hsiung HUANG Tsai-Ming HSIEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/04/01
Vol. E93-A  No. 4 ; pp. 761-768
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
level shiftermultiple supply voltagelow powervoltage assignmentinteger linear programming
 Summary | Full Text:PDF(1MB)

A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design
Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hyeokjong LEE Toshihiro KONISHI Koh TSURUDA Yasuharu SAKAI Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 261-269
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
cross-layer designsensor networkssensor nodeMAC protocoltime synchronizationlow power
 Summary | Full Text:PDF(1.6MB)

A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory
Myounggon KANG Ki-Tae PARK Youngsun SONG Sungsoo LEE Yunheub SONG Young-Ho LIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/02/01
Vol. E93-C  No. 2 ; pp. 182-186
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
NANDFLASHrow decoderhigh voltage switchlow voltagearea scalinglow power
 Summary | Full Text:PDF(583.6KB)

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability
Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3016-3023
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
low powerleakagegate delay modelvariation
 Summary | Full Text:PDF(1.1MB)

Ultra Low Power Delay Element with Post-Chip Adjustable Ability
Jung-Lin YANG Chih-Wei CHAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3381-3389
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
asynchronous circuitsbundled-datadelay-elementself-timedlow power
 Summary | Full Text:PDF(934KB)

Low-Power Embedded Processor Design Using Branch Direction
Gi-Ho PARK Jung-Wook PARK Gunok JUNG Shin-Dug KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3180-3181
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
low powerBTBwordline gating
 Summary | Full Text:PDF(344.2KB)

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation
Kazunaga HYODO Kengo IWAMOTO Hideki ANDO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/11/01
Vol. E92-D  No. 11 ; pp. 2186-2195
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
microarchitecturemicroprocessorinstruction pre-executionlow power
 Summary | Full Text:PDF(520.3KB)

A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems
Young-Ju KIM Kyung-Hoon LEE Myung-Hwan LEE Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/09/01
Vol. E92-C  No. 9 ; pp. 1194-1200
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCCMOShigh resolutionlow voltagelow powercascode compensation
 Summary | Full Text:PDF(1.6MB)

A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator
Socheat HENG Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/09/01
Vol. E92-C  No. 9 ; pp. 1208-1214
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
over current protectionlimiting currentholding currentlow dropout regulatorlow powerlow voltage
 Summary | Full Text:PDF(426.9KB)

A Low Power Reconfigurable Channel Filter Using Multi-Band and Masking Architecture for Channel Adaptation in Cognitive Radio
K. G. SMITHA A. P. VINOD 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1424-1432
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
cognitive radiochannel adaptationmulti-band filtermasking filterchannel filterlow complexitylow powerreconfigurability
 Summary | Full Text:PDF(285.9KB)

Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
Takatsugu ONO Koji INOUE Kazuaki MURAKAMI Kenji YOSHIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 433-443
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
low powervariable line-sizeon-chip DRAMhigh bandwidthembedded systems
 Summary | Full Text:PDF(497.8KB)

A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter
Shunsuke OKURA Tetsuro OKURA Toru IDO Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/02/01
Vol. E92-A  No. 2 ; pp. 367-373
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
CMOSpipelined ADCsettlingboostlow power
 Summary | Full Text:PDF(429.7KB)

Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3596-3606
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesislow powerinterconnection networkgenetic algorithm
 Summary | Full Text:PDF(1.2MB)

Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method
K.G. SMITHA A.P. VINOD 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/11/01
Vol. E91-A  No. 11 ; pp. 3282-3292
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
low powerlow complexityhigher order FIR filterscommon subexpression elimination
 Summary | Full Text:PDF(240.7KB)

Power and Skew Aware Point Diffusion Clock Network
Gunok JUNG Chunghee KIM Kyoungkuk CHAE Giho PARK Sung Bae PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/11/01
Vol. E91-C  No. 11 ; pp. 1832-1834
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
clock networkskewlatencylow power
 Summary | Full Text:PDF(868KB)

Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications
Takefumi YOSHIKAWA Tetsuhiro OGINO Makoto NAGATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/09/01
Vol. E91-C  No. 9 ; pp. 1453-1462
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation)
Category: 
Keyword: 
interfacecurrent modelow powerlow EMI noise
 Summary | Full Text:PDF(2MB)

Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers
Jimson MATHEW R. MAHESH A.P. VINOD Edmund M-K. LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/09/01
Vol. E91-A  No. 9 ; pp. 2564-2570
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
wireless communication receiverchannelizerFIR filterbinary subexpression eliminationlow power
 Summary | Full Text:PDF(682.7KB)

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
Liangpeng GUO Yici CAI Qiang ZHOU Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8 ; pp. 2084-2090
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
voltage islandlevel converterlow powerplacement
 Summary | Full Text:PDF(348.8KB)

55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers
Tomohiko ITO Daisuke KUROSE Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/06/01
Vol. E91-C  No. 6 ; pp. 887-893
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/DADCpipelinelow poweramplifierpseudo-differential amplifierI/Q sharing
 Summary | Full Text:PDF(970.9KB)

Extended MPEG Video Format for Efficient Dynamic Voltage Scaling
Kwanhu BANG Sung-Yong BANG Eui-Young CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/05/01
Vol. E91-A  No. 5 ; pp. 1283-1287
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
low powerenergyDVSvideodecodingMPEG
 Summary | Full Text:PDF(170.1KB)

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer
Yuichiro MURACHI Junichi MIYAKOSHI Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Fang YIN Jangchung LEE Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 465-478
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
low powermotion estimationH.264systolic arrayMBAFFSRAM
 Summary | Full Text:PDF(1.8MB)

Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory
Seong-Ook JUNG Sei-Seung YOON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/03/01
Vol. E91-A  No. 3 ; pp. 895-898
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
content addressable memoryhigh speedlow powerserial CAMparallel CAMhybrid CAM
 Summary | Full Text:PDF(224.3KB)

Constant Magnetic Field Scaling in Inductive-Coupling Data Link
Daisuke MIZOGUCHI Noriyuki MIURA Hiroki ISHIKURO Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/02/01
Vol. E91-C  No. 2 ; pp. 200-205
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
inductive couplingconstant magnetic fieldlow powerhigh data rateSiP
 Summary | Full Text:PDF(701.9KB)

Self-Resetting Level-Conversion Flip-Flops with Direct Output Feedback for Dual-Supply SoCs
Joo-Seong KIM Bai-Sun KONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/02/01
Vol. E91-C  No. 2 ; pp. 240-243
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
level converterclustered voltage scalingself-prechargingconditional capturelow power
 Summary | Full Text:PDF(449.2KB)

A Patterned Preamble MAC Protocol for Wireless Sensor Networks
Inwhee JOE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2008/02/01
Vol. E91-B  No. 2 ; pp. 658-661
Type of Manuscript:  LETTER
Category: Wireless Communication Technologies
Keyword: 
patterned preambleMACwireless sensor networkslow powerchannel utilization
 Summary | Full Text:PDF(506.5KB)

A 12 b 200 kS/s 0.52 mA 0.47 mm2 Algorithmic A/D Converter for MEMS Applications
Young-Ju KIM Hee-Cheol CHOI Seung-Hoon LEE Dongil "Dan" CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/02/01
Vol. E91-C  No. 2 ; pp. 206-212
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
algorithmiclow powerMEMSADCCMOS
 Summary | Full Text:PDF(590.3KB)

A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of fOSC to VDD
Felix TIMISCHL Takahiro INOUE Akio TSUNEDA Daisuke MASUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 504-512
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
CMOSring oscillatorlow powergm-boosterVDD-dependencycomposite transistorfigure of merit
 Summary | Full Text:PDF(334.1KB)

An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management
Shih-Hsu HUANG Chun-Hua CHENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/01/01
Vol. E91-A  No. 1 ; pp. 375-382
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-level synthesisinteger linear programmingschedulinglow power
 Summary | Full Text:PDF(231KB)

Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's
Doo-Hwan KIM Sung-Hyun YANG Kyoung-Rok CHO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/01/01
Vol. E91-C  No. 1 ; pp. 72-80
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
LVDSlow powerlow voltagedifferential signalI/O interface
 Summary | Full Text:PDF(1.3MB)

360-µW/1 mW Complementary Cross-Coupled Differential Colpitts LC-VCO/QVCO in 0.25-µm CMOS
Jong-Phil HONG Seok-Ju YUN Sang-Gug LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/12/01
Vol. E90-C  No. 12 ; pp. 2289-2292
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
CMOScross-coupled Colpitts oscillatorlow powerquadrature VCOvoltage controlled oscillator (VCO)
 Summary | Full Text:PDF(392.8KB)

A Low Power Real-Time Packet Scheduling Scheme on Wireless Local Area Networks
Mikyung KANG Dong-In KANG Jinwoo SUH Junghoon LEE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2007/12/01
Vol. E90-B  No. 12 ; pp. 3501-3504
Type of Manuscript:  Special Section LETTER (Special Section on Ubiquitous Sensor Networks)
Category: 
Keyword: 
low powerreal-time packet schedulingdynamic modulation schemereclaiming schemeEDF
 Summary | Full Text:PDF(233.6KB)

VLSI Implementation of a 44-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic
Yasuhiro TAKAHASHI Toshikazu SEKINE Michio YOKOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 2002-2006
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: 
Keyword: 
adiabatic logicmultiplierlow powertwo-phase power supply
 Summary | Full Text:PDF(431KB)

A Power Modeling and Optimization Scheme for Future Ultra Small Size Electric Systems
Masahiro FUKUI Sayaka IWAKOSHI Tatsuya KOYAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1900-1908
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: Low-Power and High-Performance VLSI Circuit Technology
Keyword: 
system operated by batterylow powerpower dissipation modelbattery model
 Summary | Full Text:PDF(868.1KB)

A 10 b 200 MS/s 1.8 mm2 83 mW 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors
Young-Ju KIM Young-Jae CHO Doo-Hwan SA Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 2037-2043
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCCMOS3-D symmetric layoutlow powerlow voltage
 Summary | Full Text:PDF(825.8KB)

Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications
O-Sam KWON Kyeong-Sik MIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/07/01
Vol. E90-C  No. 7 ; pp. 1540-1543
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
level shifterlow powerhigh speeddynamic voltage scalinglow voltage
 Summary | Full Text:PDF(188.7KB)

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration
Yibo WANG Yici CAI Xianlong HONG Yi ZOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5 ; pp. 1028-1037
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
interconnect optimizationaccurate delay modellow powerbuffer insertion
 Summary | Full Text:PDF(353.7KB)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI
Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 765-771
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
SOIcapacitorlessDRAMlow powerdata retention
 Summary | Full Text:PDF(932.3KB)

A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's
Fayez Robert SALIBA Hiroshi KAWAGUCHI Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 743-748
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
active leakagelow powerSRAM
 Summary | Full Text:PDF(994KB)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link
Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 829-835
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Analog and Communications
Keyword: 
low powerdaisy chaininductive couplingwide bandwidth
 Summary | Full Text:PDF(1.7MB)

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS
Kazutami ARIMOTO Toshihiro HATTORI Hidehiro TAKATA Atsushi HASEGAWA Toru SHIMIZU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 657-665
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: 
Keyword: 
low powerpower managementDSPSIMD
 Summary | Full Text:PDF(1.8MB)

CMOS Level Converter with Balanced Rise and Fall Delays
Min-su KIM Young-Hyun JUN Sung-Bae PARK Bai-Sun KONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1 ; pp. 192-195
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
level convertervoltage scalingclocklow power
 Summary | Full Text:PDF(1.4MB)

A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline
Kentaro KAWAKAMI Jun TAKEMURA Mitsuhiko KURODA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3642-3651
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
H.264/AVCDVS (dynamic voltage scaling)elastic pipelinelow powerdivided entropy decoder
 Summary | Full Text:PDF(1.3MB)

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture
Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3623-3633
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationH.264SIMDsystolic array
 Summary | Full Text:PDF(1.9MB)

A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond
Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3634-3641
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
SRAMDVSVth-variation-tolerantlow power
 Summary | Full Text:PDF(1.2MB)

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing
Junichi MIYAKOSHI Yuichiro MURACHI Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1629-1636
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
SRAMlow powerparallel processingimage signal processingH.264MPEG
 Summary | Full Text:PDF(1.7MB)

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic
Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1620-1628
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
100-Gbps Ethernetnetwork processorcachenetwork trafficlow power
 Summary | Full Text:PDF(1.7MB)

Noise Immunity Investigation of Low Power Design Schemes
Mohamed ABBAS Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/08/01
Vol. E89-C  No. 8 ; pp. 1238-1247
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
noise immunitylow powerpower supply noisedigital design
 Summary | Full Text:PDF(626.6KB)

Multi-Standard CMOS LC QVCO with Reconfigurable LC Tank and Low Power Low Phase Noise Quadrature Generation Method
Ji-Hoon KIM Hyung-Joun YOO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/06/01
Vol. E89-A  No. 6 ; pp. 1547-1551
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005))
Category: 
Keyword: 
multi-standardCMOS LC QVCOreconfigurable LC tanklow powerlow phase noisequadrature generation method
 Summary | Full Text:PDF(747.3KB)

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era
Kazutoshi KOBAYASHI Akihiko HIGUCHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/06/01
Vol. E89-C  No. 6 ; pp. 838-843
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
sleep transistordecoupling capacitorMTCMOSlow power
 Summary | Full Text:PDF(442KB)

An Embedded 8b 240 MS/s 1.36 mm2 104 mW 0.18 µm CMOS ADC for DVDs with Dual-Mode Inputs
Young-Jae CHO Se-Won KIM Kyung-Hoon LEE Hee-Cheol CHOI Young-Lok KIM Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/05/01
Vol. E89-C  No. 5 ; pp. 636-641
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCCMOSlow powersmall areaon-chip I/V references
 Summary | Full Text:PDF(1MB)

A 10b 100 MS/s 1.4 mm2 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors
Byoung-Han MIN Young-Jae CHO Hee-Sung CHAE Hee-Won PARK Seung-Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/05/01
Vol. E89-C  No. 5 ; pp. 630-635
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
ADCCMOSlow poweron-chip referencespipeline
 Summary | Full Text:PDF(1.3MB)

Low Power Block-Based Watermarking Algorithm
Yu-Ting PAI Shanq-Jang RUAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1507-1514
Type of Manuscript:  PAPER
Category: Application Information Security
Keyword: 
digital watermarkdata hidingcopyright protectionlow powerdiscrete cosine transform
 Summary | Full Text:PDF(1.9MB)

A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy
Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 902-907
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
CMOSsensorsubthresholdtranslinearlow powerquality guarantee
 Summary | Full Text:PDF(598.5KB)

Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond
Koichiro ISHIBASHI Tetsuya FUJIMOTO Takahiro YAMASHITA Hiroyuki OKADA Yukio ARIMA Yasuyuki HASHIMOTO Kohji SAKATA Isao MINEMATSU Yasuo ITOH Haruki TODA Motoi ICHIHASHI Yoshihide KOMATSU Masato HAGIWARA Toshiro TSUKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 250-262
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
low powerCMOSSoC90 nmlow voltagevariability
 Summary | Full Text:PDF(2.1MB)

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology
Daisuke MIZOGUCHI Noriyuki MIURA Takayasu SAKURAI Tadahiro KURODA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 320-326
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Interface and Interconnect Techniques
Keyword: 
inductive couplingwireless superconnect3D-stacked chipslow powerhigh bandwidth
 Summary | Full Text:PDF(904KB)

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping
Canh Quang TRAN Hiroshi KAWAGUCHI Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 280-286
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Low Power Techniques
Keyword: 
FPGAlow powerlow leakageVDD hoppingZigzag power-gating
 Summary | Full Text:PDF(952.1KB)

Low Power Low Phase Noise LC Quadrature VCO Topology
Ji-Hoon KIM Hyung-Joun YOO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 440-442
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
LC QVCOlow powerlow phase noise
 Summary | Full Text:PDF(221.4KB)

A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits
Masakazu SHIMIZU Koki ABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/01/01
Vol. E89-A  No. 1 ; pp. 280-287
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
asynchronous circuitsbundled-data stylehandshake protocolslow power
 Summary | Full Text:PDF(1.7MB)

Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era
Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Jun TAKEMURA Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3290-3297
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
low powerdynamic voltage frequency scaling (DVFS)adaptive body biasingVdd-hoppingVth-hopping
 Summary | Full Text:PDF(686.3KB)

Quality and Power Efficient Architecture for the Discrete Cosine Transform
Chi-Chia SUNG Shanq-Jang RUAN Bo-Yao LIN Mon-Chau SHIE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3500-3507
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
Loeffler DCTbinDCTDAASSIMlow power
 Summary | Full Text:PDF(579.6KB)

A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application
Yuichiro MURACHI Koji HAMANO Tetsuro MATSUNO Junichi MIYAKOSHI Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3492-3499
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
low powermotion estimationMPEG2HDTVIP
 Summary | Full Text:PDF(1.7MB)

Frequency-Scaling Approach for Managing Power Consumption in NOCs
Chun-Lung HSU Wen-Tso WANG Ying-Fu HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3580-3583
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
frequency-scalinglow powerNOCFPGA
 Summary | Full Text:PDF(486.7KB)

Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy
Hidekazu TANAKA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3274-3281
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
low powercacheway predictionconfidence information
 Summary | Full Text:PDF(1MB)

Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications
Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3282-3289
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
bus encodingECC/EDClow powerreliability
 Summary | Full Text:PDF(560.9KB)

A CMOS Low-Noise Amplifier for Ultra Wideband Wireless Applications
Mei-Fen CHOU Wen-Shen WUEN Chang-Ching WU Kuei-Ann WEN Chun-Yen CHANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11 ; pp. 3110-3117
Type of Manuscript:  Special Section PAPER (Special Section on Wide Band Systems)
Category: 
Keyword: 
low noise amplifierultra-widebandstagger tuning techniquelow power
 Summary | Full Text:PDF(777.8KB)

A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
Jianping HU Tiefeng XU Hong LI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1479-1485
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
register filelow poweradiabatic logicVLSI design
 Summary | Full Text:PDF(646KB)

Noise Metrics in Flip-Flop Designs
Mohammed A. ELGAMEL Md Ibrahim FAISAL Magdy A. BAYOUMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1501-1505
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
flip-flopnoise immunitylow powerdeep aubmicron
 Summary | Full Text:PDF(284.6KB)

Ultralow-Power Current Reference Circuit with Low Temperature Dependence
Tetsuya HIROSE Toshimasa MATSUOKA Kenji TANIGUCHI Tetsuya ASAI Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/06/01
Vol. E88-C  No. 6 ; pp. 1142-1147
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit and Device Technologies)
Category: Building Block
Keyword: 
CMOSreferencesubthresholdweak inversionlow powertemperature dependence
 Summary | Full Text:PDF(378.8KB)

A Temperature and Supply Voltage Independent CMOS Voltage Reference Circuit
Toshihiro MATSUDA Ryuichi MINAMI Akira KANAMORI Hideyuki IWATA Takashi OHZONE Shinya YAMAMOTO Takashi IHARA Shigeki NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5 ; pp. 1087-1093
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
CMOSvoltage referencethreshold-voltagelow power
 Summary | Full Text:PDF(953.5KB)

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 862-868
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powercacheleakage
 Summary | Full Text:PDF(1014.7KB)

A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters
Toru TANZAWA Kenichi AGAWA Hiroyuki SHIBAYAMA Ryota TERAUCHI Katsumi HISANO Hiroki ISHIKURO Shouhei KOUSAI Hiroyuki KOBAYASHI Hideaki MAJIMA Toru TAKAYAMA Masayuki KOIZUMI Fumitoshi HATORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 490-495
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Analog
Keyword: 
GFSKCMOS LC-VCOBluetoothdirect modulationlow power
 Summary | Full Text:PDF(3.1MB)

CMOS Radio Design for Complete Single Chip GPS SoC
Norihito SUZUKI Takahide KADOYAMA Masayuki KATAKURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 496-501
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Analog
Keyword: 
GPSradioCMOSSoCsubstrate coupling noiselow power
 Summary | Full Text:PDF(1012KB)

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 552-558
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
parallel processingVLIWSMTlow powernanometerleakage power
 Summary | Full Text:PDF(1.1MB)

A Low-Power, Small-Size 10-Bit Successive-Approximation ADC
Mehdi BANIHASHEMI Khayrollah HADIDI Abdollah KHOEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 996-1006
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
successive-approximation ADClow power
 Summary | Full Text:PDF(1.2MB)

A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones
Makoto ISHIKAWA Tatsuya KAMEI Yuki KONDO Masanao YAMAOKA Yasuhisa SHIMAZAKI Motokazu OZAWA Saneaki TAMAKI Mikio FURUYAMA Tadashi HOSHI Fumio ARAKAWA Osamu NISHII Kenji HIROSE Shinichi YOSHIOKA Toshihiro HATTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 528-535
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
application processorcellular phonepipeline structureresume-standbylow powerlow leakage
 Summary | Full Text:PDF(1.3MB)

Coupling-Driven Data Bus Encoding for SoC Video Architectures
Luca FANUCCI Riccardo LOCATELLI Andrea MINGHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3083-3090
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
bus encodingdeep sub-micronlow powersystem-on-chipvideo codingvery large scale integration architectures
 Summary | Full Text:PDF(898.5KB)

A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI
Kazuki FUKUOKA Masaaki IIJIMA Kenji HAMADA Masahiro NUMA Akira TADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3244-3250
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Floorplan
Keyword: 
dual supply voltageslow powerbody-tied PD-SOI
 Summary | Full Text:PDF(468.6KB)

High-Level Power Optimization Based on Thread Partitioning
Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3075-3082
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
high-level synthesislow powerthread partitioninggated clocks
 Summary | Full Text:PDF(436.6KB)

A Low-Power High-Frequency CMOS Current-Mirror Sinusoidal Quadrature Oscillator
Adisorn LEELASANTITHAM Banlue SRISUCHINWONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/11/01
Vol. E87-A  No. 11 ; pp. 2964-2972
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
sinusoidal quadrature oscillatorCMOS current mirrorsnegative resistancelow powerfigure of merits
 Summary | Full Text:PDF(1.8MB)

Reconfigurable Logic Family Based on Floating Gates
Luis Fortino CISNEROS-SINENCIO Alejandro DIAZ-SANCHEZ Jaime RAMIREZ-ANGULO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1884-1888
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
logic familylow-voltagelow powersmall-areafloating-gate transistors
 Summary | Full Text:PDF(320.7KB)

Low Area and Low Power Structures of DCT-Based Noise Generation System
Dae-Ik KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/09/01
Vol. E87-A  No. 9 ; pp. 2466-2470
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
low arealow powerDCTcentral limit theorem
 Summary | Full Text:PDF(1.1MB)

A 300-mW Programmable QAM Transceiver for VDSL Applications
Hyoungsik NAM Tae Hun KIM Yongchul SONG Jae Hoon SHIM Beomsup KIM Yong Hoon LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/08/01
Vol. E87-C  No. 8 ; pp. 1367-1375
Type of Manuscript:  PAPER
Category: Microwaves, Millimeter-Waves
Keyword: 
very-high-speed digital subscriber lineprogrammable QAM transceiverIIR notch filterdual loop AGClow power
 Summary | Full Text:PDF(872.4KB)

A Design for Testability Technique for Low Power Delay Fault Testing
James Chien-Mo LI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 621-628
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
testability technology (design for testability)delay fault testinglow powerASIC
 Summary | Full Text:PDF(1.2MB)

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori MUROYAMA Akihiko HYODO Takanori OKUMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 598-605
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
active bitlow powerdatapathdata busdynamic
 Summary | Full Text:PDF(421.1KB)

Circuit Partition and Reordering Technique for Low Power IP Design
Kun-Lin TSAI Shanq-Jang RUAN Chun-Ming HUANG Edwin NAROSKA Feipei LAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 613-620
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low powerstate reorderingcircuit partitionentropy
 Summary | Full Text:PDF(483.3KB)

A Low-Power Microcontroller with Body-Tied SOI Technology
Hisakazu SATO Yasuhiro NUNOMURA Niichi ITOH Koji NII Kanako YOSHIDA Hironobu ITO Jingo NAKANISHI Hidehiro TAKATA Yasunobu NAKASE Hiroshi MAKINO Akira YAMADA Takahiko ARAKAWA Toru SHIMIZU Yuichi HIRANO Takashi IPPOSHI Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 563-570
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
low powerhigh speedmicrocontrollerSOI
 Summary | Full Text:PDF(1.3MB)

A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter
Fumitoshi HATORI Hiroki ISHIKURO Mototsugu HAMADA Ken-ichi AGAWA Shouhei KOUSAI Hiroyuki KOBAYASHI Duc Minh NGUYEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 556-562
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
Bluetoothwireless communicationCMOS transceiverlow-IFdirect modulationlow power
 Summary | Full Text:PDF(917.8KB)

A Novel Static Prediction Scheme for Filter Cache Structures
Kugan VIVEKANANDARAJAH Thambipillai SRIKANTHAN Christopher T. CLARKE Saurav BHATTACHARYYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 543-548
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
filter-cachestatic pattern predictionNFPTlow power
 Summary | Full Text:PDF(323.4KB)

A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU
Hideo OHIRA Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Masayuki MIYAMA Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 457-465
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEG4 encoderlow powerfeed-forward voltage controlmulti-regulated voltage CPU
 Summary | Full Text:PDF(1.9MB)

A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor
Toshihiro HATTORI Kenji OGURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 520-526
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
threshold voltagelow powerdual-Vthphysical synthesis
 Summary | Full Text:PDF(935.5KB)

VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding
Masayuki MIYAMA Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 466-474
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEGmotion estimationgradient based methodsteepest descent methodlow powerVLSI
 Summary | Full Text:PDF(731.6KB)

Low Voltage and Low Power CMOS Exponential-Control Variable-Gain Amplifier
Weihsing LIU Shen-Iuan LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A  No. 4 ; pp. 952-954
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
CMOSlow voltagelow powerexponential-controlVGA
 Summary | Full Text:PDF(268.9KB)

Perspectives of Low-Power VLSI's
Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 429-436
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
digitalmemoryapplicationlow powerVLSIleakage
 Summary | Full Text:PDF(1.7MB)

A New Solution to Power Supply Voltage Drop Problems in Scan Testing
Takaki YOSHIDA Masafumi WATARI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 580-585
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Scan Testing
Keyword: 
power supply voltage dropnoiselow powerscan testclock duty
 Summary | Full Text:PDF(923.9KB)

Power Analysis and Estimation for SOC Design: Techniques and Tools
Yun CAO Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/02/01
Vol. E87-A  No. 2 ; pp. 410-416
Type of Manuscript:  REVIEW PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerSOCpower analysispower estimation
 Summary | Full Text:PDF(248.6KB)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs
Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 2991-3000
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Power Optimization
Keyword: 
embedded memoryDRAMlow powersystem on chip
 Summary | Full Text:PDF(2.9MB)

A 90 mW MPEG-4 Video Codec LSI with the Capability for Core Profile
Takashi HASHIMOTO Shunichi KUROMARU Masayoshi TOUJIMA Yasuo KOHASHI Masatoshi MATSUO Toshihiro MORIIWA Masahiro OHASHI Tsuyoshi NAKAMURA Mana HAMADA Yuji SUGISAWA Miki KUROMARU Tomonori YONEZAWA Satoshi KAJITA Takahiro KONDO Hiroki OTSUKI Kohkichi HASHIMOTO Hiromasa NAKAJIMA Taro FUKUNAGA Hiroaki TOIDA Yasuo IIZUKA Hitoshi FUJIMOTO Junji MICHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/07/01
Vol. E86-C  No. 7 ; pp. 1374-1384
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
MPEG-4 visualcore profilehybrid architectureclock gatingembedded DRAMlow power
 Summary | Full Text:PDF(2.3MB)

High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors
Hiroshi TAKAHASHI Rimon IKENO Yutaka TOYONOH Akihiro TAKEGAMA Yasumasa IKEZAKI Tohru URASAKI Hitoshi SATOH Masayasu ITOIGAWA Yoshinari MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 589-596
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
high speedlow powerfixed point DSP160 MHz0.18 µm
 Summary | Full Text:PDF(1.7MB)

Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4 ; pp. 799-805
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powerinstruction ROMembedded systemsencoding
 Summary | Full Text:PDF(710.3KB)

Low Power Motion Estimation and Motion Compensation Block IPs in MPEG-4 Video Codec Hardware for Portable Applications
Chi-Weon YOON Hoi-Jun YOO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 553-560
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
low powermotion estimationmotion compensationMPEG-4
 Summary | Full Text:PDF(947.8KB)

A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit
Hiromi NOTANI Masayuki KOYAMA Ryuji MANO Hiroshi MAKINO Yoshio MATSUDA Osamu TOMISAWA Shuhei IWADE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 597-603
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
low powerstandby currentbackgate controlMT-CMOS
 Summary | Full Text:PDF(829.6KB)

8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region
Jun TERADA Yasuyuki MATSUYA Fumiharu MORISAWA Yuichi KADO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2 ; pp. 313-317
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
A/D converterlow voltagelow powerbubble errormonotonicity
 Summary | Full Text:PDF(694.8KB)

Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems
Takashi YAMADA Shoji GOTO Norihisa TAKAYAMA Yoshifumi MATSUSHITA Yasoo HARADA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/01/01
Vol. E86-C  No. 1 ; pp. 79-88
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
matched filterspread-spectrumWCDMAVLSIlow power
 Summary | Full Text:PDF(987.9KB)

A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
Keiichi KUROKAWA Takuya YASUI Yoichi MATSUMURA Masahiko TOYONAGA Atsushi TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2746-2755
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Clock Scheduling
Keyword: 
clock schedulingclock tree synthesishigh-speedlow power
 Summary | Full Text:PDF(1.4MB)

A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver
Tatsuji MATSUURA Junya KUDOH Eiki IMAIZUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/08/01
Vol. E85-C  No. 8 ; pp. 1538-1545
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits)
Category: 
Keyword: 
A/D converterCMOSlow powerpipelineBluetooth
 Summary | Full Text:PDF(1MB)

A 0.99 µA Operating Current Li-Ion Battery Protection IC
Yen-Shyung SHYU Jiin-Chuan WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/05/01
Vol. E85-C  No. 5 ; pp. 1211-1215
Type of Manuscript:  LETTER
Category: Optoelectronics
Keyword: 
Li-ion batteryprotection IClow powerbandgap voltage
 Summary | Full Text:PDF(238.2KB)

Adaptive Bitwidth Compression for Low Power Video Memory Design
Vasily MOSHNYAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 797-803
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
bit-compressionlow powervideo memoryadaptive technique
 Summary | Full Text:PDF(655.5KB)

Development of a CMOS Data Recovery PLL for DVD-ROMx14
Shiro DOSHO Naoshi YANAGISAWA Seiji WATANABE Takahiro BOKUI Kazuhiko NISHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 764-769
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
DVD-ROMdata recoveryjitter detectorlow powerfrequency detector
 Summary | Full Text:PDF(537.1KB)

A Controller LSI for Realizing VDD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System
Hiroshi KAWAGUCHI Gang ZHANG Seongsoo LEE Youngsoo SHIN Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 263-271
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
low powerreal-time embedded systemdynamic voltage scalingapplication slicingMPEG4
 Summary | Full Text:PDF(1.5MB)

Trends in High-Performance, Low-Power Cache Memory Architectures
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 304-314
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
cachelow powerhigh performancemicroprocessorsurvey
 Summary | Full Text:PDF(238.5KB)

SIMD ISA Extensions: Power Efficiency on Multimedia on a Superscalar Processor
Julien SEBOT Nathalie DRACH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 297-303
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
multimediaSIMDsuperscalarlow power
 Summary | Full Text:PDF(465.8KB)

Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 279-287
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
cachelow powerlook uprun time
 Summary | Full Text:PDF(726.5KB)

Wide-Input Range Linear Voltage-to-Current Converter Using Equivalent MOSFETs without Cutoff Region
Kazuyuki WADA Shigetaka TAKAGI Nobuo FUJII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2 ; pp. 347-353
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
voltage-to-current converterlow voltageinput rangelow powerequivalent MOSFET
 Summary | Full Text:PDF(439.1KB)

A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
Tetsuya YAMADA Makoto ISHIKAWA Yuji OGATA Takanobu TSUNODA Takahiro IRITA Saneaki TAMAKI Kunihiko NISHIYAMA Tatsuya KAMEI Ken TATEZAWA Fumio ARAKAWA Takuichiro NAKAZAWA Toshihiro HATTORI Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 253-262
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processorlow powerRISCDSPMAC
 Summary | Full Text:PDF(1.8MB)

Issue Queue Energy Reduction through Dynamic Voltage Scaling
Vasily G. MOSHNYAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 272-278
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
issue queuecomputer architecturelow powervoltage scaling
 Summary | Full Text:PDF(365KB)

Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1 ; pp. 234-240
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerglitchgate sizingbuffer insertion
 Summary | Full Text:PDF(1.6MB)

Motion Estimation Using Edge Enhanced Low-Bit Images for Lowpower MPEG Encoder
Ayuko TAKAGI Kiyoshi NISHIKAWA Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/08/01
Vol. E84-A  No. 8 ; pp. 1900-1908
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Image/Visual Signal Processing
Keyword: 
low powermotion estimationMPEGlow-bit imageedge enhancement
 Summary | Full Text:PDF(629.6KB)

Selective Clock Suppression of Protocol Modules for a Low Power Protocol Converter
Young Moo LEE Kyu Ho PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/07/01
Vol. E84-D  No. 7 ; pp. 906-909
Type of Manuscript:  LETTER
Category: Computer System Element
Keyword: 
CMOS digital integrated circuitlow powerprotocol conversion
 Summary | Full Text:PDF(344.7KB)

Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 399-409
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion estimationlow bit resolutionVLSI architectureparallelismlow power
 Summary | Full Text:PDF(815.1KB)

Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs
Fukashi MORISHITA Kazutami ARIMOTO Kazuyasu FUJISHIMA Hideyuki OZAKI Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 253-259
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SOIfloating bodybody controlhigh speedlow power
 Summary | Full Text:PDF(497.4KB)

A Low Power Media Processor Core Performable CIF30 fr/s MPEG4/H26x Video Codec
Hideo OHIRA Toshihisa KAMEMARU Hirokazu SUZUKI Ken-ichi ASANO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 157-165
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLSImedia processor corevideo codinglow powerhigh performance
 Summary | Full Text:PDF(521.6KB)

Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS
Naoki KATO Yohei AKITA Mitsuru HIRAKI Takeo YAMASHITA Teruhisa SHIMIZU Fuyuhiko MAKI Kazuo YANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1747-1754
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
CMOSthreshold voltageleakage currentlow power
 Summary | Full Text:PDF(1.2MB)

A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1716-1723
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
cachelow powervariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1001.2KB)

A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications
Hae-Moon SEO Chang-Gene WOO Sang-Won OH Sung-Wook JUNG Pyung CHOI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1720-1727
Type of Manuscript:  PAPER
Category: General Fundamentals and Boundaries
Keyword: 
parallel clock and data recoveryCMOSoptical communicationslow power
 Summary | Full Text:PDF(1.1MB)

Motion Estimation with Power Scalability and Its VHDL Model
Ayuko TAKAGI Shogo MURAMATSU Hitoshi KIYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1608-1613
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
low powermotion estimationMPEGless gray level image
 Summary | Full Text:PDF(826.9KB)

Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias
Toshiro HIRAMOTO Makoto TAKAMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2 ; pp. 161-169
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
MOSFETlow powerlow voltagevariable threshold voltageback-biasbody effectDTMOSSOI
 Summary | Full Text:PDF(887.3KB)

A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2 ; pp. 186-194
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
cachelow powerlow energyway predictionhigh performance
 Summary | Full Text:PDF(1015.4KB)

Approaches for Reducing Power Consumption in VLSI Bus Circuits
Kunihiro ASADA Makoto IKEDA Satoshi KOMATSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2 ; pp. 153-160
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
low powerreduced signal swingsignal transition reductionbus encoding/decodingtime-domain circuitminimum Hamming-distance detector
 Summary | Full Text:PDF(1.4MB)

A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/01/25
Vol. E83-C  No. 1 ; pp. 109-114
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
cacheSRAMlow powertwo-portmicroprocessor
 Summary | Full Text:PDF(1.4MB)

A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops
Won-Hyo LEE Sung-Dae LEE Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2514-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
PFDcharge-pumplow powerPLLhigh speedD flip-floperror detection range
 Summary | Full Text:PDF(807.5KB)

A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive
Jin-Cheon KIM Sang-Hoon LEE Hong-June PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1777-1779
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
CMOS flip-floplow powerhalf-swing clockingcomplementary drive
 Summary | Full Text:PDF(252.9KB)

Low-Power Scheme of NMOS 4-Phase Dynamic Logic
Bao-Yu SONG Makoto FURUIE Yukihiro YOSHIDA Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1772-1776
Type of Manuscript:  Special Section LETTER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Low-Power Circuit Technique
Keyword: 
low power4-phase dynamic logicshort-circuit currentsmall voltage swing
 Summary | Full Text:PDF(730.1KB)

A 1-V, 1-Vp-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors
Koichi TANNO Okihiko ISHIZUKA Zheng TANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/05/25
Vol. E82-C  No. 5 ; pp. 750-757
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
multiplierlow voltagelow powerneuron MOS transistoranalog integrated circuit
 Summary | Full Text:PDF(435KB)

Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM
Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3 ; pp. 544-552
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
SOI-DRAMfloating bodyhigh speedlow powerdata retention characteristics
 Summary | Full Text:PDF(592.4KB)

A Flip-Flop Circuit with a Directly Controlled Emitter-Follower and a Level Stabilizer for Low-Power Prescalers
Hisayasu SATO Nagisa SASAKI Takahiro MIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3 ; pp. 504-510
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
prescalerflip-flopemitter-followerlow power
 Summary | Full Text:PDF(432.8KB)

High Frequency Characteristics of Dynamic Threshold-Voltage MOSFET (DTMOS) under Ultra-Low Supply Voltage
Tetsu TANAKA Youichi MOMIYAMA Toshihiro SUGII 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/03/25
Vol. E82-C  No. 3 ; pp. 538-543
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology)
Category: Silicon Devices
Keyword: 
SOIDTMOSFtFmaxlow power
 Summary | Full Text:PDF(709.9KB)

Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture
Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/01/25
Vol. E82-C  No. 1 ; pp. 94-104
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMmacrocellsize-configurablehigh speedlow powerper-bitline architecturecurrent-sense amplifiersquashed memory celltrench isolation
 Summary | Full Text:PDF(931.1KB)

Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches
Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2621-2629
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Compiler
Keyword: 
compiler optimizationinstruction schedulinglow powercaches
 Summary | Full Text:PDF(762.4KB)

Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic
Minkyu SONG Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/11/25
Vol. E81-C  No. 11 ; pp. 1740-1749
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
power saved pass-transistor logic (PSPL)low powerregenerative feedback5454-bit multiplier7-bit serial counter
 Summary | Full Text:PDF(1.1MB)

Three Dimensional Image Analysis of Multi-Field Driving Method for Reducing Multi-Media LCD Power Consumption
Haruhiko OKUMURA Goh ITOH 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/11/25
Vol. E81-C  No. 11 ; pp. 1691-1696
Type of Manuscript:  Special Section PAPER (Special Issue on Electronic Displays)
Category: 
Keyword: 
driving methodmulti-medialow powerTFT-LCD
 Summary | Full Text:PDF(456.4KB)

Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application
Koichi TANNO Okihiko ISHIZUKA Zheng TANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/10/25
Vol. E81-A  No. 10 ; pp. 2194-2200
Type of Manuscript:  PAPER
Category: Analog Signal Processing
Keyword: 
virtual-shortweak-inversion regionlow powerlow voltageCMOS analog circuitintegrated circuit
 Summary | Full Text:PDF(565.6KB)

Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs
Taku OHSAWA Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1455-1462
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
DRAMDRAM refreshmerged DRAM/logicsystem LSIlow power
 Summary | Full Text:PDF(737.9KB)

A Fast Frequency Switching Synthesizer with a Digitally Controlled Delay Generator
Hideyuki NOSAKA Tadao NAKAGAWA Akihiro YAMAGISHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/07/25
Vol. E81-A  No. 7 ; pp. 1466-1472
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals of Multi-dimensional Mobile Information Network)
Category: 
Keyword: 
direct digital synthesizerfrequency synthesizerlow powerspread spectrumfrequency hoppingspurious signals
 Summary | Full Text:PDF(533.2KB)

Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM
Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 759-767
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
integration of DRAM and logicembedded DRAMlow powerhigh memory bandwidth
 Summary | Full Text:PDF(951.7KB)

An LSI for Low Bit-Rate Image Compression Using Vector Quantization
Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 718-724
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
parallel processormemory-basedvector quantizationlow bit-rate image compressionlow powerSIMD
 Summary | Full Text:PDF(748.2KB)

Bipartition and Synthesis in Low Power Pipelined Circuits
Shyh-Jong CHEN Rung-Ji SHANG Xian-June HUANG Shang-Jang RUAN Feipei LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 664-671
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
bipartitionsynthesislow powergated-clockpipelined circuit
 Summary | Full Text:PDF(793.8KB)

Low Power Management Method for PDS ONU Logic LSIs
Koichi SAITO Kiyoshi MATSUMOTO Kennosuke FUKAMI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/03/25
Vol. E81-B  No. 3 ; pp. 604-608
Type of Manuscript:  PAPER
Category: Communication Device and Circuit
Keyword: 
LSIlogic LSIlow powerPDSONU
 Summary | Full Text:PDF(487KB)

10 µA Quiescent Current Opamp Design for LCD Driver ICs
Tetsuro ITAKURA Hironori MINAMIZAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/02/25
Vol. E81-A  No. 2 ; pp. 230-236
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era)
Category: 
Keyword: 
analog circuits and signal processingintegrated electronics CMOS opamplow power
 Summary | Full Text:PDF(595KB)

Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH
Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1539-1545
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
RISCarchitecturelow powerhigh speedmicroprocessor
 Summary | Full Text:PDF(674.5KB)

A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's
Nobutaro SHIBATA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1598-1607
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
SRAMlow powervirtual GNDcolumn addresssynchronousmacrocell
 Summary | Full Text:PDF(774.4KB)

A 100 MIPS High Speed and Low Power Digital Signal Processor
Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuji OZAWA Kenichi TASHIRO Shigetoshi MURAMATSU Masahiro FUSUMADA Akemi TODOROKI Youichi TANAKA Masayasu ITOIGAWA Isao MORIOKA Hiroyuki MIZUNO Miki KOJIMA Giovanni NASO Emmanuel EGO Frank CHIRAT 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1546-1552
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
100 MIPSdigital signal processinghigh speedlow powerCPU
 Summary | Full Text:PDF(750.2KB)

Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview
Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/12/25
Vol. E80-C  No. 12 ; pp. 1511-1522
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies)
Category: 
Keyword: 
Si bipolarhigh speedlow poweroptical transmission
 Summary | Full Text:PDF(954.7KB)

Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis
Ho-Yup KWON Koji KOTANI Tadashi SHIBATA Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 924-930
Type of Manuscript:  Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs)
Category: Novel Concept Devices
Keyword: 
neuron MOSdeep-thresholdlow powerfull addernumber detector
 Summary | Full Text:PDF(514.5KB)

A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD
Hiroyasu YOSHIZAWA Kenji TANIGUCHI Hiroyuki SHIRAHAMA Kenichi NAKASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/06/25
Vol. E80-A  No. 6 ; pp. 1015-1020
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96))
Category: 
Keyword: 
PLLPFDVCOlow powersource couplingdynamic circuit
 Summary | Full Text:PDF(516.8KB)

The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications
Yuichi KADO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3 ; pp. 443-454
Type of Manuscript:  INVITED PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: Circuit Technologies and Applications
Keyword: 
CMOSSOISIMOXlow voltagelow power
 Summary | Full Text:PDF(898.5KB)

Design of a Low-Voltage, Low-Power, High-Frequency CMOS Current-Mode VCO Circuit by Using 0.6µm MOS Devices
Yasuhiro SUGIMOTO Takeshi UENO Takaaki TSUJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/02/25
Vol. E80-A  No. 2 ; pp. 304-312
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
Category: 
Keyword: 
CMOS VCOcurrent-mode circuitlow voltagelow powerhigh-frequency
 Summary | Full Text:PDF(638.8KB)

An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors
Yasuhisa SHIMAZAKI Katsuhiro NORISUE Koichiro ISHIBASHI Hideo MAEJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12 ; pp. 1693-1698
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
RISC microprocessorcache memorylow power
 Summary | Full Text:PDF(651.5KB)

Low Power Multi-Media TFT-LCD Using Multi-Field Driving Method
Haruhiko OKUMURA Goh ITOH Kouhei SUZUKI Kouji SUZUKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/08/25
Vol. E79-C  No. 8 ; pp. 1109-1111
Type of Manuscript:  Special Section LETTER (Special Issue on Liquid-Crystal Displays)
Category: 
Keyword: 
driving methodmulti-medialow powerTFT-LCDinterlace scan
 Summary | Full Text:PDF(313KB)

A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits
Hisayuki HIGUCHI Suguru TACHIBANA Masataka MINAMI Takahiro NAGANO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 757-762
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
TLBCAMlow powerfully associative
 Summary | Full Text:PDF(624.5KB)

A 1.3 V Supply Voltage AlGaAs/InGaAs HJFET SCFL D-FF Operating at up to 10 Gbps
Masahiro FUJII Tadashi MAEDA Yasuo OHNO Masatoshi TOKUSHIMA Masaoki ISHIKAWA Muneo FUKAISHI Hikaru HIDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4 ; pp. 512-517
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
low powerhigh speedGaAsheterojunction FETSCFLlogic swinglow supply voltageD-FF
 Summary | Full Text:PDF(698.8KB)

Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors
Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/03/25
Vol. E79-C  No. 3 ; pp. 424-429
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
low powerpartitioned-bus architecturevariable-width-bus schememicroprocessor
 Summary | Full Text:PDF(513.1KB)

A Current-Mode Bit-Block Circuit Applicable to Low-Voltage, Low-Power Pipeline Video-Speed A/D Converters
Yasuhiro SUGIMOTO Shunsaku TOKITO Hisao KAKITANI Eitaro SETA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/02/25
Vol. E79-A  No. 2 ; pp. 199-209
Type of Manuscript:  Special Section PAPER (Special Section on Analog Technologies in Submicron Era)
Category: 
Keyword: 
ADC bit-block circuitcurrent-mode circuitpipeline-type ADCvideo-speed ADClow voltagelow power
 Summary | Full Text:PDF(810.2KB)

A Low-Power and High-Speed Impulse-Transmission CMOS Interface Circuit
Masafumi NOGAWA Yusuke OHTOMO Masayuki INO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1733-1737
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
CMOSlow-voltage swinginterfacelow powerhigh speedimpulse transmission
 Summary | Full Text:PDF(394.7KB)

A Circuit Library for Low Power and High Speed Digital Signal Processor
Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1717-1725
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
low powerhigh speedlow costGSMPDCNADCdigital signal processingpersonal communication50 MIPSCPU
 Summary | Full Text:PDF(903.7KB)

Low-power LSI Circuit Technologies for Portable Terminal Equipment
Shoji HORIGUCHI Tsuneo TSUKAHARA Hideki FUKUDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/12/25
Vol. E78-C  No. 12 ; pp. 1655-1667
Type of Manuscript:  INVITED PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
Category: 
Keyword: 
low voltagelow powerportable terminal equipmentmulti-threshold CMOS
 Summary | Full Text:PDF(1004.1KB)

Data Bypassing Register File for Low Power Microprocessor
Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/10/25
Vol. E78-C  No. 10 ; pp. 1470-1472
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
low powerdata bypassing register filemicroprocessorimplicit data bypassing scheme
 Summary | Full Text:PDF(259.9KB)

High Speed GaAs Digital Integrated Circuits
Masahiro AKIYAMA Seiji NISHI Yasushi KAWAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/09/25
Vol. E78-C  No. 9 ; pp. 1165-1170
Type of Manuscript:  INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices)
Category: 
Keyword: 
GaAs digital ICDCFLSBFLhigh speedlow powerself-alignment processrecessed gate processcircuit designstandard cell
 Summary | Full Text:PDF(534.1KB)

A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits
Nobutaro SHIBATA Mayumi WATANABE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 797-804
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
marcocellmemorysynchronouslow powerlatch type
 Summary | Full Text:PDF(712KB)

Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization
Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 441-446
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: DA/Architecture
Keyword: 
LSIlayouttransistor sizinglow powerCAD
 Summary | Full Text:PDF(608.5KB)

An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors
Masakazu YAMASHINA Hachiro YAMADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10 ; pp. 1181-1187
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: Low-Voltage Operation
Keyword: 
current mode logiclow powerhigh speedMOS
 Summary | Full Text:PDF(519.1KB)