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Keyword : low power

A Dual-Mode Deblocking Filter Design for HEVC and H.264/AVC Muchen LI¡Ê9999999¡Ë Waseda University¡¨Jinjia ZHOU¡Ê9999999¡Ë Waseda University¡¨Dajiang ZHOU¡Ê9999999¡Ë Waseda University¡¨Xiao PENG¡Ê9999999¡Ë Waseda University¡¨Satoshi GOTO¡Ê6803632¡Ë Waseda University
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-A No. 6 pp. 1366-1375 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: HEVC, H.264/AVC, deblocking filter, dual-mode, low power, SHV, HD,
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A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer Teerachot SIRIBURANON¡Ê9999999¡Ë Tokyo Institute of Technology¡¨Takahiro SATO¡Ê9999999¡Ë Tokyo Institute of Technology¡¨Ahmed MUSA¡Ê9999999¡Ë Tokyo Institute of Technology¡¨Wei DENG¡Ê9999999¡Ë Tokyo Institute of Technology¡¨Kenichi OKADA¡Ê0014397¡Ë Tokyo Institute of Technology¡¨Akira MATSUZAWA¡Ê8116598¡Ë Tokyo Institute of Technology
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/06/01 Vol. E96-C No. 6 pp. 804-812 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: low phase noise, low power, tail-current modulation, impulse sensitivity function, super-harmonic coupled QVCO, push-push VCO,
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Valid Digit and Overflow Information to Reduce Energy Dissipation of Functional Units in General Purpose Processors Kazuhito ITO Takuya NUMATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/04/01 Vol. E96-C No. 4 pp. 463-472 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology) Category: Keyword: low power, functional unit, narrow operand,
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A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method Hyuk-Jun LEE Seung-Chul KIM Eui-Young CHUNG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2013/04/01 Vol. E96-D No. 4 pp. 963-966 Type of Manuscript: LETTER Category: Computer System Keyword: router, packet memory, low power, TCP,
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A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor Networks Mitsuo NAKAMURA Mamoru UGAJIN Mitsuru HARADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2013/01/01 Vol. E96-C No. 1 pp. 93-101 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: intra-symbol intermittent, RF front end, low power, wireless receiver, RF CMOS, sensor network,
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RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path Yukihiro SASAGAWA Jun YAO Takashi NAKADA Yasuhiko NAKASHIMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2319-2329 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: adaptive redundancy, setup error recovery, DVS, low power, AVF,
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Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System Haiqi WANG Sheqin DONG Tao LIN Song CHEN Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2208-2219 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: dual-vdd, min-cut, voltage assignment, low power, timing constraints,
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Region Oriented Routing FPGA Architecture for Dynamic Power Gating Ce LI Yiping DONG Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/12/01 Vol. E95-A No. 12 pp. 2199-2207 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: FPGA, low power, switch box, routing,
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A Novel 400-Gb/s (100-Gb/s4) Physical-Layer Architecture Using Low-Power Technology Masashi KONO Akihiro KANBE Hidehiro TOYODA Shinji NISHIMURA
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2012/11/01 Vol. E95-B No. 11 pp. 3437-3444 Type of Manuscript: PAPER Category: Transmission Systems and Transmission Equipment for Communications Keyword: Ethernet, low power, physical layer, single-wavelength transmission,
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Low Power Clock Gating for Shift Register Ki-Sung SOHN Da-In HAN Ki-Ju BAEK Nam-Soo KIM Yeong-Seuk KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/08/01 Vol. E95-C No. 8 pp. 1447-1448 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: low power, small area, clock gating circuit,
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A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF) Xiayu LI Song JIA Limin LIU Yuan WANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/06/01 Vol. E95-C No. 6 pp. 1125-1127 Type of Manuscript: BRIEF PAPER Category: Electronic Circuits Keyword: flip-flop, pulse generator free, high speed, low power,
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Low Power Nonvolatile Counter Unit with Fine-Grained Power Gating Shuta TOGASHI Takashi OHSAWA Tetsuo ENDOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/05/01 Vol. E95-C No. 5 pp. 854-859 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices) Category: Keyword: MTJ, nonvolatile, fine-grained power gating, counter unit, low power,
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Low-Power Circuit Applicability of Hetero-Gate-Dielectric Tunneling Field-Effect Transistors (HG TFETs) Gibong LEE Woo Young CHOI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/05/01 Vol. E95-C No. 5 pp. 910-913 Type of Manuscript: BRIEF PAPER Category: Keyword: low power, propagation delay, energy dissipation, tunneling field-effect transistor (TFET),
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A Trace-Back Method with Source States for Viterbi Decoding of Rate-1/n Convolutional Codes Kazuhito ITO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2012/04/01 Vol. E95-A No. 4 pp. 767-775 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: Viterbi decoder, convolutional code, trace back, survivor memory, low power,
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An Energy-Efficient Full Adder Cell Using CNFET Technology Mohammad Reza RESHADINEZHAD Mohammad Hossein MOAIYERI Kaivan NAVI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 744-751 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: CNFET, Full adder, High performance, low power, nanotechnology,
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A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring Hirofumi IWATO Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/04/01 Vol. E95-C No. 4 pp. 487-494 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology) Category: Keyword: pressure sensing, urinary bladder, SoC, low power, ASIP,
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CMOS Differential Circuits Using Charge-Redistribution and Reduced-Swing Schemes Hong-Yi HUANG Shiun-Dian JAN Yang CHOU Cheng-Yu CHEN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/02/01 Vol. E95-C No. 2 pp. 275-283 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: differential logic, charge redistribution, low power, high speed, multiplier-accumulator,
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Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture Ce LI Yiping DONG Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/02/01 Vol. E95-D No. 2 pp. 314-323 Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems) Category: Design Methodology Keyword: FPGA, low power, region, hierarchical design, power consumption,
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A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling Byung-Do YANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2676-2684 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: charge-recycling, DC-DC conversion, low power, on-chip,
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Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture Ce LI Yiping DONG Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/12/01 Vol. E94-A No. 12 pp. 2519-2527 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Physical Level Design Keyword: FPGA, low power, power domain, power consumption,
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A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio Toshihiro KONISHI Shintaro IZUMI Koh TSURUDA Hyeokjong LEE Takashi TAKEUCHI Masahiko YOSHIMOTO Hiroshi KAWAGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/11/01 Vol. E94-A No. 11 pp. 2287-2294 Type of Manuscript: Special Section PAPER (Special Section on Smart Multimedia & Communication Systems) Category: Mobile Information Network and Personal Communications Keyword: MRSS, multi-resolution spectrum sensing, cognitive radio, wireless sensor network, low power,
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An Adaptive Various-Width Data Cache for Low Power Design Jiongyao YE Yu WAN Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/08/01 Vol. E94-D No. 8 pp. 1539-1546 Type of Manuscript: PAPER Category: Computer System Keyword: low power, data cache, frequent values, narrow-width values,
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A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques Byeong-Woo KOO Seung-Jae PARK Gil-Cho AHN Seung-Hoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/08/01 Vol. E94-C No. 8 pp. 1282-1288 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: ADC, pipeline, low power, SHA-free, circuit sharing, two-step reference selection,
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Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism Jiongyao YE Yingtao HU Hongfeng DING Takahiro WATANABE
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/07/01 Vol. E94-D No. 7 pp. 1398-1408 Type of Manuscript: PAPER Category: Computer System Keyword: low power, instruction cache, instruction fetch mechanism,
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A 1-Mbps 1.6-µA Active-RFID CMOS LSI for the 300-MHz Frequency Band with an All-Digital RF Transmitting Scheme Kenji SUZUKI Mamoru UGAJIN Mitsuru HARADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/06/01 Vol. E94-C No. 6 pp. 1084-1090 Type of Manuscript: PAPER Category: Microwaves, Millimeter-Waves Keyword: active tags, RFID, VHF, low power, transmitter, OOK, wireless sensor networks,
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Low Power Platform for Embedded Processor LSIs Toru SHIMIZU Kazutami ARIMOTO Osamu NISHII Sugako OTANI Hiroyuki KONDO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 394-400 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: INVITED Keyword: low power, processor, operating system, distributed processing,
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Multiple Region-of-Interest Based H.264 Encoder with a Detection Architecture in Macroblock Level Pipelining Tianruo ZHANG Chen LIU Minghui WANG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 401-410 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: H.264 encoding, VLSI architecture, region-of-interest, low power,
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Low Power Bus Binding Exploiting Optimal Substructure Ji-Hyung KIM Jun-Dong CHO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/01/01 Vol. E94-A No. 1 pp. 332-341 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: low power, bus binding, switching activity, table decomposition, optimal substructure,
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A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS Yanfei CHEN Sanroku TSUKAMOTO Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2600-2608 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Design Keyword: ADC, successive approximation, charge redistribution, calibration, low power,
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Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating Xin MAN Takashi HORIYAMA Shinji KIMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2472-2480 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: automatic clock gating generation, low power, dynamic power reduction, BDD,
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Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems Tetsuo YOKOYAMA Gang ZENG Hiroyuki TOMIYAMA Hiroaki TAKADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2010/10/01 Vol. E93-D No. 10 pp. 2737-2746 Type of Manuscript: PAPER Category: Software System Keyword: battery-aware voltage scheduling, dynamic voltage scaling, low power, real-time systems,
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A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment Benjamin STEFAN DEVLIN Toru NAKURA Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/07/01 Vol. E93-A No. 7 pp. 1319-1328 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: self synchronous, fpga, pipeline alignment, low power, high throughput, dynamic logic, dual pipeline,
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A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS Lechang LIU Zhiwei ZHOU Takayasu SAKURAI Makoto TAKAMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 796-802 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: impulse radio ultra-wideband (IR-UWB), charge-domain sampling correlators, charge injection, variable threshold comparator, low power,
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An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder Sung-Jin KIM Minchang CHO SeongHwan CHO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/06/01 Vol. E93-C No. 6 pp. 785-795 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: EPCglobal, Class 1, Generation 2, RFID, RFID tag, pulse interval encoded, passive, low power, PIE decoder, calibration,
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A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power Applications Katsumi DOSAKA Daisuke OGAWA Takahito KUSUMOTO Masayuki MIYAMA Yoshio MATSUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/05/01 Vol. E93-C No. 5 pp. 685-695 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: TCAM, charge recycling, low power, low noise, low operating current,
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A Low Complexity Low Power Signal Transition Detector Design for Self-Timed Circuits Jin-Fa LIN Yin-Tsung HWANG Ming-Hwa SHEU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/04/01 Vol. E93-A No. 4 pp. 843-845 Type of Manuscript: LETTER Category: Circuit Theory Keyword: signal transition detection, pulse generation, self-timed circuit, low power,
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Optimal Supply Voltage Assignment under Timing, Power and Area Constraints Hsi-An CHIEN Cheng-Chiang LIN Hsin-Hsiung HUANG Tsai-Ming HSIEH
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/04/01 Vol. E93-A No. 4 pp. 761-768 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: level shifter, multiple supply voltage, low power, voltage assignment, integer linear programming,
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A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design Shintaro IZUMI Takashi TAKEUCHI Takashi MATSUDA Hyeokjong LEE Toshihiro KONISHI Koh TSURUDA Yasuharu SAKAI Hiroshi KAWAGUCHI Chikara OHTA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 261-269 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: cross-layer design, sensor networks, sensor node, MAC protocol, time synchronization, low power,
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A Low Power and Area Scalable High Voltage Switch Technique for Low Operation Voltage in MLC NAND Flash Memory Myounggon KANG Ki-Tae PARK Youngsun SONG Sungsoo LEE Yunheub SONG Young-Ho LIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/02/01 Vol. E93-C No. 2 pp. 182-186 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: NAND, FLASH, row decoder, high voltage switch, low voltage, area scaling, low power,
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Low-Power Embedded Processor Design Using Branch Direction Gi-Ho PARK Jung-Wook PARK Gunok JUNG Shin-Dug KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3180-3181 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: low power, BTB, wordline gating,
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Ultra Low Power Delay Element with Post-Chip Adjustable Ability Jung-Lin YANG Chih-Wei CHAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3381-3389 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: asynchronous circuits, bundled-data, delay-element, self-timed, low power,
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An Approach for Reducing Leakage Current Variation due to Manufacturing Variability Tsuyoshi SAKATA Takaaki OKUMURA Atsushi KUROKAWA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO Koutaro HACHIYA Katsuhiro FURUKAWA Masakazu TANAKA Hiroshi TAKAFUJI Toshiki KANAMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-A No. 12 pp. 3016-3023 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: low power, leakage, gate delay model, variation,
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Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation Kazunaga HYODO Kengo IWAMOTO Hideki ANDO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2009/11/01 Vol. E92-D No. 11 pp. 2186-2195 Type of Manuscript: PAPER Category: Computer Systems Keyword: microarchitecture, microprocessor, instruction pre-execution, low power,
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A Low-Power High Accuracy Over Current Protection Circuit for Low Dropout Regulator Socheat HENG Cong-Kha PHAM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/09/01 Vol. E92-C No. 9 pp. 1208-1214 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: over current protection, limiting current, holding current, low dropout regulator, low power, low voltage,
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A 0.31 pJ/Conversion-Step 12-Bit 100 MS/s 0.13 µm CMOS A/D Converter for 3G Communication Systems Young-Ju KIM Kyung-Hoon LEE Myung-Hwan LEE Seung-Hoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/09/01 Vol. E92-C No. 9 pp. 1194-1200 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: ADC, CMOS, high resolution, low voltage, low power, cascode compensation,
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A Low Power Reconfigurable Channel Filter Using Multi-Band and Masking Architecture for Channel Adaptation in Cognitive Radio K. G. SMITHA A. P. VINOD
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1424-1432 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: cognitive radio, channel adaptation, multi-band filter, masking filter, channel filter, low complexity, low power, reconfigurability,
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Reducing On-Chip DRAM Energy via Data Transfer Size Optimization Takatsugu ONO Koji INOUE Kazuaki MURAKAMI Kenji YOSHIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/04/01 Vol. E92-C No. 4 pp. 433-443 Type of Manuscript: Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era) Category: Keyword: low power, variable line-size, on-chip DRAM, high bandwidth, embedded systems,
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A Reference Voltage Buffer with Settling Boost Technique for a 12 bit 18 MHz Multibit/Stage Pipelined A/D Converter Shunsuke OKURA Tetsuro OKURA Toru IDO Kenji TANIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/02/01 Vol. E92-A No. 2 pp. 367-373 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: CMOS, pipelined ADC, settling, boost, low power,
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Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages Hasitha Muthumala WAIDYASOORIYA Masanori HARIYAMA Michitaka KAMEYAMA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3596-3606 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: High-Level Synthesis and System-Level Design Keyword: high-level synthesis, low power, interconnection network, genetic algorithm,
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Low Power Realization and Synthesis of Higher-Order FIR Filters Using an Improved Common Subexpression Elimination Method K.G. SMITHA A.P. VINOD
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/11/01 Vol. E91-A No. 11 pp. 3282-3292 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: low power, low complexity, higher order FIR filters, common subexpression elimination,
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Power and Skew Aware Point Diffusion Clock Network Gunok JUNG Chunghee KIM Kyoungkuk CHAE Giho PARK Sung Bae PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/11/01 Vol. E91-C No. 11 pp. 1832-1834 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: clock network, skew, latency, low power,
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Current-Mode Transceiver with Nonfeedback Clock Recovery Capability for Mobile Applications Takefumi YOSHIKAWA Tetsuhiro OGINO Makoto NAGATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/09/01 Vol. E91-C No. 9 pp. 1453-1462 Type of Manuscript: Special Section PAPER (Special Section on Advanced Processors Based on Novel Concepts in Computation) Category: Keyword: interface, current mode, low power, low EMI noise,
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Realization of Low Power High-Speed Channel Filters with Stringent Adjacent Channel Attenuation Specifications for Wireless Communication Receivers Jimson MATHEW R. MAHESH A.P. VINOD Edmund M-K. LAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2564-2570 Type of Manuscript: PAPER Category: Digital Signal Processing Keyword: wireless communication receiver, channelizer, FIR filter, binary subexpression elimination, low power,
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Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage Liangpeng GUO Yici CAI Qiang ZHOU Xianlong HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/08/01 Vol. E91-A No. 8 pp. 2084-2090 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: voltage island, level converter, low power, placement,
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55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers Tomohiko ITO Daisuke KUROSE Takeshi UENO Takafumi YAMAJI Tetsuro ITAKURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/06/01 Vol. E91-C No. 6 pp. 887-893 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: A/D, ADC, pipeline, low power, amplifier, pseudo-differential amplifier, I/Q sharing,
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Extended MPEG Video Format for Efficient Dynamic Voltage Scaling Kwanhu BANG Sung-Yong BANG Eui-Young CHUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/05/01 Vol. E91-A No. 5 pp. 1283-1287 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: low power, energy, DVS, video, decoding, MPEG,
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A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer Yuichiro MURACHI Junichi MIYAKOSHI Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Fang YIN Jangchung LEE Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 465-478 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: low power, motion estimation, H.264, systolic array, MBAFF, SRAM,
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Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory Seong-Ook JUNG Sei-Seung YOON
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/03/01 Vol. E91-A No. 3 pp. 895-898 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: content addressable memory, high speed, low power, serial CAM, parallel CAM, hybrid CAM,
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A Patterned Preamble MAC Protocol for Wireless Sensor Networks Inwhee JOE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2008/02/01 Vol. E91-B No. 2 pp. 658-661 Type of Manuscript: LETTER Category: Wireless Communication Technologies Keyword: patterned preamble, MAC, wireless sensor networks, low power, channel utilization,
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Self-Resetting Level-Conversion Flip-Flops with Direct Output Feedback for Dual-Supply SoCs Joo-Seong KIM Bai-Sun KONG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/02/01 Vol. E91-C No. 2 pp. 240-243 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: level converter, clustered voltage scaling, self-precharging, conditional capture, low power,
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Constant Magnetic Field Scaling in Inductive-Coupling Data Link Daisuke MIZOGUCHI Noriyuki MIURA Hiroki ISHIKURO Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/02/01 Vol. E91-C No. 2 pp. 200-205 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: inductive coupling, constant magnetic field, low power, high data rate, SiP,
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A 12 b 200 kS/s 0.52 mA 0.47 mm² Algorithmic A/D Converter for MEMS Applications Young-Ju KIM Hee-Cheol CHOI Seung-Hoon LEE Dongil "Dan" CHO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/02/01 Vol. E91-C No. 2 pp. 206-212 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: algorithmic, low power, MEMS, ADC, CMOS,
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A New Low-Power 13.56-MHz CMOS Ring Oscillator with Low Sensitivity of f_OSC to V_DD Felix TIMISCHL Takahiro INOUE Akio TSUNEDA Daisuke MASUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/02/01 Vol. E91-A No. 2 pp. 504-512 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: CMOS, ring oscillator, low power, g_m-booster, V_DD-dependency, composite transistor, figure of merit,
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Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's Doo-Hwan KIM Sung-Hyun YANG Kyoung-Rok CHO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/01/01 Vol. E91-C No. 1 pp. 72-80 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: LVDS, low power, low voltage, differential signal, I/O interface,
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An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management Shih-Hsu HUANG Chun-Hua CHENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/01/01 Vol. E91-A No. 1 pp. 375-382 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: high-level synthesis, integer linear programming, scheduling, low power,
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360-µW/1 mW Complementary Cross-Coupled Differential Colpitts LC-VCO/QVCO in 0.25-µm CMOS Jong-Phil HONG Seok-Ju YUN Sang-Gug LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/12/01 Vol. E90-C No. 12 pp. 2289-2292 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: CMOS, cross-coupled Colpitts oscillator, low power, quadrature VCO, voltage controlled oscillator (VCO),
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A Low Power Real-Time Packet Scheduling Scheme on Wireless Local Area Networks Mikyung KANG Dong-In KANG Jinwoo SUH Junghoon LEE
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2007/12/01 Vol. E90-B No. 12 pp. 3501-3504 Type of Manuscript: Special Section LETTER (Special Section on Ubiquitous Sensor Networks) Category: Keyword: low power, real-time packet scheduling, dynamic modulation scheme, reclaiming scheme, EDF,
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A Power Modeling and Optimization Scheme for Future Ultra Small Size Electric Systems Masahiro FUKUI Sayaka IWAKOSHI Tatsuya KOYAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1900-1908 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: system operated by battery, low power, power dissipation model, battery model,
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VLSI Implementation of a 44-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic Yasuhiro TAKAHASHI Toshikazu SEKINE Michio YOKOYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 2002-2006 Type of Manuscript: Special Section LETTER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Keyword: adiabatic logic, multiplier, low power, two-phase power supply,
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A 10 b 200 MS/s 1.8 mm² 83 mW 0.13 µm CMOS ADC Based on Highly Linear Integrated Capacitors Young-Ju KIM Young-Jae CHO Doo-Hwan SA Seung-Hoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 2037-2043 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: ADC, CMOS, 3-D symmetric layout, low power, low voltage,
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Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications O-Sam KWON Kyeong-Sik MIN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/07/01 Vol. E90-C No. 7 pp. 1540-1543 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: level shifter, low power, high speed, dynamic voltage scaling, low voltage,
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Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration Yibo WANG Yici CAI Xianlong HONG Yi ZOU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/05/01 Vol. E90-A No. 5 pp. 1028-1037 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: interconnect optimization, accurate delay model, low power, buffer insertion,
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Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS Kazutami ARIMOTO Toshihiro HATTORI Hidehiro TAKATA Atsushi HASEGAWA Toru SHIMIZU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 657-665 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: INVITED Keyword: low power, power management, DSP, SIMD,
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A Self-Alignment Row-by-Row Variable-V_DD Scheme Reducing 90% of Active-Leakage Power in SRAM's Fayez Robert SALIBA Hiroshi KAWAGUCHI Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 743-748 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: active leakage, low power, SRAM,
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A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI Fukashi MORISHITA Hideyuki NODA Isamu HAYASHI Takayuki GYOHTEN Mako OKAMOTO Takashi IPPOSHI Shigeto MAEGAWA Katsumi DOSAKA Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 765-771 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Memory Keyword: SOI, capacitorless, DRAM, low power, data retention,
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Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 829-835 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Analog and Communications Keyword: low power, daisy chain, inductive coupling, wide bandwidth,
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CMOS Level Converter with Balanced Rise and Fall Delays Min-su KIM Young-Hyun JUN Sung-Bae PARK Bai-Sun KONG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/01/01 Vol. E90-C No. 1 pp. 192-195 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: level converter, voltage scaling, clock, low power,
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A 0.3-V Operating, V_th-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond Yasuhiro MORITA Hidehiro FUJIWARA Hiroki NOGUCHI Kentaro KAWAKAMI Junichi MIYAKOSHI Shinji MIKAMI Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3634-3641 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: SRAM, DVS, V_th-variation-tolerant, low power,
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A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture Junichi MIYAKOSHI Yuichiro MURACHI Tetsuro MATSUNO Masaki HAMAMOTO Takahiro IINUMA Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3623-3633 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: low power, motion estimation, H.264, SIMD, systolic array,
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A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline Kentaro KAWAKAMI Jun TAKEMURA Mitsuhiko KURODA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3642-3651 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: H.264/AVC, DVS (dynamic voltage scaling), elastic pipeline, low power, divided entropy decoder,
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Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1620-1628 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: 100-Gbps Ethernet, network processor, cache, network traffic, low power,
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A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing Junichi MIYAKOSHI Yuichiro MURACHI Tomokazu ISHIHARA Hiroshi KAWAGUCHI Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1629-1636 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: Keyword: SRAM, low power, parallel processing, image signal processing, H.264, MPEG,
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Noise Immunity Investigation of Low Power Design Schemes Mohamed ABBAS Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/08/01 Vol. E89-C No. 8 pp. 1238-1247 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: noise immunity, low power, power supply noise, digital design,
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Multi-Standard CMOS LC QVCO with Reconfigurable LC Tank and Low Power Low Phase Noise Quadrature Generation Method Ji-Hoon KIM Hyung-Joun YOO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/06/01 Vol. E89-A No. 6 pp. 1547-1551 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2005 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2005)) Category: Keyword: multi-standard, CMOS LC QVCO, reconfigurable LC tank, low power, low phase noise, quadrature generation method,
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A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era Kazutoshi KOBAYASHI Akihiko HIGUCHI Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 838-843 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: sleep transistor, decoupling capacitor, MTCMOS, low power,
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An Embedded 8b 240 MS/s 1.36 mm² 104 mW 0.18 µm CMOS ADC for DVDs with Dual-Mode Inputs Young-Jae CHO Se-Won KIM Kyung-Hoon LEE Hee-Cheol CHOI Young-Lok KIM Seung-Hoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/05/01 Vol. E89-C No. 5 pp. 636-641 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: ADC, CMOS, low power, small area, on-chip I/V references,
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A 10b 100 MS/s 1.4 mm² 56 mW 0.18 µm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors Byoung-Han MIN Young-Jae CHO Hee-Sung CHAE Hee-Won PARK Seung-Hoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/05/01 Vol. E89-C No. 5 pp. 630-635 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: ADC, CMOS, low power, on-chip references, pipeline,
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Low Power Block-Based Watermarking Algorithm Yu-Ting PAI Shanq-Jang RUAN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/04/01 Vol. E89-D No. 4 pp. 1507-1514 Type of Manuscript: PAPER Category: Application Information Security Keyword: digital watermark, data hiding, copyright protection, low power, discrete cosine transform,
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A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 902-907 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: CMOS, sensor, subthreshold, translinear, low power, quality guarantee,
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Low Power Low Phase Noise LC Quadrature VCO Topology Ji-Hoon KIM Hyung-Joun YOO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 440-442 Type of Manuscript: LETTER Category: Electronic Circuits Keyword: LC QVCO, low power, low phase noise,
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A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology Daisuke MIZOGUCHI Noriyuki MIURA Takayasu SAKURAI Tadahiro KURODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 320-326 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interface and Interconnect Techniques Keyword: inductive coupling, wireless superconnect, 3D-stacked chips, low power, high bandwidth,
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Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V_TH/V_DD and Micro-V_DD-Hopping Canh Quang TRAN Hiroshi KAWAGUCHI Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 280-286 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Low Power Techniques Keyword: FPGA, low power, low leakage, V_DD hopping, Zigzag power-gating,
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Low-Voltage and Low-Power Logic, Memory, and Analog Circuit Techniques for SoCs Using 90 nm Technology and Beyond Koichiro ISHIBASHI Tetsuya FUJIMOTO Takahiro YAMASHITA Hiroyuki OKADA Yukio ARIMA Yasuyuki HASHIMOTO Kohji SAKATA Isao MINEMATSU Yasuo ITOH Haruki TODA Motoi ICHIHASHI Yoshihide KOMATSU Masato HAGIWARA Toshiro TSUKADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 250-262 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: INVITED Keyword: low power, CMOS, SoC, 90 nm, low voltage, variability,
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A Cost-Effective Handshake Protocol and Its Implementation for Bundled-Data Asynchronous Circuits Masakazu SHIMIZU Koki ABE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/01/01 Vol. E89-A No. 1 pp. 280-287 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: asynchronous circuits, bundled-data style, handshake protocols, low power,
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A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application Yuichiro MURACHI Koji HAMANO Tetsuro MATSUNO Junichi MIYAKOSHI Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3492-3499 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: low power, motion estimation, MPEG2, HDTV, IP,
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Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications Satoshi KOMATSU Masahiro FUJITA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3282-3289 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: bus encoding, ECC/EDC, low power, reliability,
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Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy Hidekazu TANAKA Koji INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3274-3281 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: low power, cache, way prediction, confidence information,
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Frequency-Scaling Approach for Managing Power Consumption in NOCs Chun-Lung HSU Wen-Tso WANG Ying-Fu HONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3580-3583 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: frequency-scaling, low power, NOC, FPGA,
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Quality and Power Efficient Architecture for the Discrete Cosine Transform Chi-Chia SUNG Shanq-Jang RUAN Bo-Yao LIN Mon-Chau SHIE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3500-3507 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Architecture Keyword: Loeffler DCT, binDCT, DAA, SSIM, low power,
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Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Jun TAKEMURA Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3290-3297 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Low Power Methodology Keyword: low power, dynamic voltage frequency scaling (DVFS), adaptive body biasing, V_dd-hopping, V_th-hopping,
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A CMOS Low-Noise Amplifier for Ultra Wideband Wireless Applications Mei-Fen CHOU Wen-Shen WUEN Chang-Ching WU Kuei-Ann WEN Chun-Yen CHANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/11/01 Vol. E88-A No. 11 pp. 3110-3117 Type of Manuscript: Special Section PAPER (Special Section on Wide Band Systems) Category: Keyword: low noise amplifier, ultra-wideband, stagger tuning technique, low power,
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Noise Metrics in Flip-Flop Designs Mohammed A. ELGAMEL Md Ibrahim FAISAL Magdy A. BAYOUMI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1501-1505 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: flip-flop, noise immunity, low power, deep aubmicron,
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A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic Jianping HU Tiefeng XU Hong LI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/07/01 Vol. E88-D No. 7 pp. 1479-1485 Type of Manuscript: Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1) Category: Digital Circuits and Computer Arithmetic Keyword: register file, low power, adiabatic logic, VLSI design,
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Ultralow-Power Current Reference Circuit with Low Temperature Dependence Tetsuya HIROSE Toshimasa MATSUOKA Kenji TANIGUCHI Tetsuya ASAI Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/06/01 Vol. E88-C No. 6 pp. 1142-1147 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Building Block Keyword: CMOS, reference, subthreshold, weak inversion, low power, temperature dependence,
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A Temperature and Supply Voltage Independent CMOS Voltage Reference Circuit Toshihiro MATSUDA Ryuichi MINAMI Akira KANAMORI Hideyuki IWATA Takashi OHZONE Shinya YAMAMOTO Takashi IHARA Shigeki NAKAJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/05/01 Vol. E88-C No. 5 pp. 1087-1093 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: CMOS, voltage reference, threshold-voltage, low power,
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CMOS Radio Design for Complete Single Chip GPS SoC Norihito SUZUKI Takahide KADOYAMA Masayuki KATAKURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 496-501 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Analog Keyword: GPS, radio, CMOS, SoC, substrate coupling noise, low power,
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A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 552-558 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: parallel processing, VLIW, SMT, low power, nanometer, leakage power,
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A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones Makoto ISHIKAWA Tatsuya KAMEI Yuki KONDO Masanao YAMAOKA Yasuhisa SHIMAZAKI Motokazu OZAWA Saneaki TAMAKI Mikio FURUYAMA Tadashi HOSHI Fumio ARAKAWA Osamu NISHII Kenji HIROSE Shinichi YOSHIOKA Toshihiro HATTORI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 528-535 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: application processor, cellular phone, pipeline structure, resume-standby, low power, low leakage,
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A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters Toru TANZAWA Kenichi AGAWA Hiroyuki SHIBAYAMA Ryota TERAUCHI Katsumi HISANO Hiroki ISHIKURO Shouhei KOUSAI Hiroyuki KOBAYASHI Hideaki MAJIMA Toru TAKAYAMA Masayuki KOIZUMI Fumitoshi HATORI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 490-495 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Analog Keyword: GFSK, CMOS LC-VCO, Bluetooth, direct modulation, low power,
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A Low-Power, Small-Size 10-Bit Successive-Approximation ADC Mehdi BANIHASHEMI Khayrollah HADIDI Abdollah KHOEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 996-1006 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: successive-approximation ADC, low power,
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Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 862-868 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power, cache, leakage,
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Coupling-Driven Data Bus Encoding for SoC Video Architectures Luca FANUCCI Riccardo LOCATELLI Andrea MINGHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3083-3090 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: bus encoding, deep sub-micron, low power, system-on-chip, video coding, very large scale integration architectures,
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A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI Kazuki FUKUOKA Masaaki IIJIMA Kenji HAMADA Masahiro NUMA Akira TADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3244-3250 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Floorplan Keyword: dual supply voltages, low power, body-tied PD-SOI,
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High-Level Power Optimization Based on Thread Partitioning Jumpei UCHIDA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/12/01 Vol. E87-A No. 12 pp. 3075-3082 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: System Level Design Keyword: high-level synthesis, low power, thread partitioning, gated clocks,
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Reconfigurable Logic Family Based on Floating Gates Luis Fortino CISNEROS-SINENCIO Alejandro DIAZ-SANCHEZ Jaime RAMIREZ-ANGULO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/11/01 Vol. E87-C No. 11 pp. 1884-1888 Type of Manuscript: Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics) Category: Keyword: logic family, low-voltage, low power, small-area, floating-gate transistors,
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A Low-Power High-Frequency CMOS Current-Mirror Sinusoidal Quadrature Oscillator Adisorn LEELASANTITHAM Banlue SRISUCHINWONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/11/01 Vol. E87-A No. 11 pp. 2964-2972 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: sinusoidal quadrature oscillator, CMOS current mirrors, negative resistance, low power, figure of merits,
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Low Area and Low Power Structures of DCT-Based Noise Generation System Dae-Ik KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/09/01 Vol. E87-A No. 9 pp. 2466-2470 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: low area, low power, DCT, central limit theorem,
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A 300-mW Programmable QAM Transceiver for VDSL Applications Hyoungsik NAM Tae Hun KIM Yongchul SONG Jae Hoon SHIM Beomsup KIM Yong Hoon LEE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/08/01 Vol. E87-C No. 8 pp. 1367-1375 Type of Manuscript: PAPER Category: Microwaves, Millimeter-Waves Keyword: very-high-speed digital subscriber line, programmable QAM transceiver, IIR notch filter, dual loop AGC, low power,
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Circuit Partition and Reordering Technique for Low Power IP Design Kun-Lin TSAI Shanq-Jang RUAN Chun-Ming HUANG Edwin NAROSKA Feipei LAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 613-620 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power, state reordering, circuit partition, entropy,
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Low Voltage and Low Power CMOS Exponential-Control Variable-Gain Amplifier Weihsing LIU Shen-Iuan LIU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/04/01 Vol. E87-A No. 4 pp. 952-954 Type of Manuscript: LETTER Category: Circuit Theory Keyword: CMOS, low voltage, low power, exponential-control, VGA,
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A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor Toshihiro HATTORI Kenji OGURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 520-526 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: threshold voltage, low power, dual-Vth, physical synthesis,
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Perspectives of Low-Power VLSI's Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 429-436 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: INVITED Keyword: digital, memory, application, low power, VLSI, leakage,
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A Feed-Forward Dynamic Voltage Control Algorithm for Low Power MPEG4 on Multi-Regulated Voltage CPU Hideo OHIRA Kentaro KAWAKAMI Miwako KANAMORI Yasuhiro MORITA Masayuki MIYAMA Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 457-465 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: MPEG4 encoder, low power, feed-forward voltage control, multi-regulated voltage CPU,
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VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding Masayuki MIYAMA Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 466-474 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: MPEG, motion estimation, gradient based method, steepest descent method, low power, VLSI,
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A Novel Static Prediction Scheme for Filter Cache Structures Kugan VIVEKANANDARAJAH Thambipillai SRIKANTHAN Christopher T. CLARKE Saurav BHATTACHARYYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 543-548 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: filter-cache, static pattern prediction, NFPT, low power,
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A Full-CMOS Single Chip Bluetooth LSI with 1.5 MHz-IF Receiver and Direct Modulation Transmitter Fumitoshi HATORI Hiroki ISHIKURO Mototsugu HAMADA Ken-ichi AGAWA Shouhei KOUSAI Hiroyuki KOBAYASHI Duc Minh NGUYEN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 556-562 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: Bluetooth, wireless communication, CMOS transceiver, low-IF, direct modulation, low power,
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A Low-Power Microcontroller with Body-Tied SOI Technology Hisakazu SATO Yasuhiro NUNOMURA Niichi ITOH Koji NII Kanako YOSHIDA Hironobu ITO Jingo NAKANISHI Hidehiro TAKATA Yasunobu NAKASE Hiroshi MAKINO Akira YAMADA Takahiko ARAKAWA Toru SHIMIZU Yuichi HIRANO Takashi IPPOSHI Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 563-570 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: low power, high speed, microcontroller, SOI,
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A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits Masanori MUROYAMA Akihiko HYODO Takanori OKUMA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 598-605 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: active bit, low power, datapath, data bus, dynamic,
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A Design for Testability Technique for Low Power Delay Fault Testing James Chien-Mo LI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2004/04/01 Vol. E87-C No. 4 pp. 621-628 Type of Manuscript: Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies) Category: Keyword: testability technology (design for testability), delay fault testing, low power, ASIC,
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A New Solution to Power Supply Voltage Drop Problems in Scan Testing Takaki YOSHIDA Masafumi WATARI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 580-585 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Scan Testing Keyword: power supply voltage drop, noise, low power, scan test, clock duty,
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Power Analysis and Estimation for SOC Design: Techniques and Tools Yun CAO Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/02/01 Vol. E87-A No. 2 pp. 410-416 Type of Manuscript: REVIEW PAPER Category: VLSI Design Technology and CAD Keyword: low power, SOC, power analysis, power estimation,
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A Low Power Embedded DRAM Macro for Battery-Operated LSIs Takeshi FUJINO Akira YAMAZAKI Yasuhiko TAITO Mitsuya KINOSHITA Fukashi MORISHITA Teruhiko AMANO Masaru HARAGUCHI Makoto HATAKENAKA Atsushi AMO Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2991-3000 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Power Optimization Keyword: embedded memory, DRAM, low power, system on chip,
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A 90 mW MPEG-4 Video Codec LSI with the Capability for Core Profile Takashi HASHIMOTO Shunichi KUROMARU Masayoshi TOUJIMA Yasuo KOHASHI Masatoshi MATSUO Toshihiro MORIIWA Masahiro OHASHI Tsuyoshi NAKAMURA Mana HAMADA Yuji SUGISAWA Miki KUROMARU Tomonori YONEZAWA Satoshi KAJITA Takahiro KONDO Hiroki OTSUKI Kohkichi HASHIMOTO Hiromasa NAKAJIMA Taro FUKUNAGA Hiroaki TOIDA Yasuo IIZUKA Hitoshi FUJIMOTO Junji MICHIYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/07/01 Vol. E86-C No. 7 pp. 1374-1384 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: MPEG-4 visual, core profile, hybrid architecture, clock gating, embedded DRAM, low power,
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Low Power Motion Estimation and Motion Compensation Block IPs in MPEG-4 Video Codec Hardware for Portable Applications Chi-Weon YOON Hoi-Jun YOO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 553-560 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Architecture and Algorithms Keyword: low power, motion estimation, motion compensation, MPEG-4,
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A Low Standby Current DSP Core Using Improved ABC-MT-CMOS with Charge Pump Circuit Hiromi NOTANI Masayuki KOYAMA Ryuji MANO Hiroshi MAKINO Yoshio MATSUDA Osamu TOMISAWA Shuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 597-603 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Circuit Design Keyword: low power, standby current, backgate control, MT-CMOS,
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High-Speed and Low-Power Techniques of Hardware and Software for Digital Signal Processors Hiroshi TAKAHASHI Rimon IKENO Yutaka TOYONOH Akihiro TAKEGAMA Yasumasa IKEZAKI Tohru URASAKI Hitoshi SATOH Masayasu ITOIGAWA Yoshinari MATSUMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 589-596 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Circuit Design Keyword: high speed, low power, fixed point DSP, 160 MHz, 0.18 µm,
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Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/04/01 Vol. E86-A No. 4 pp. 799-805 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power, instruction ROM, embedded systems, encoding,
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8-mW, 1-V, 100-MSample/s, 6-bit A/D Converter Using a Latched Comparator Operating in the Triode Region Jun TERADA Yasuyuki MATSUYA Fumiharu MORISAWA Yuichi KADO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/02/01 Vol. E86-A No. 2 pp. 313-317 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: A/D converter, low voltage, low power, bubble error, monotonicity,
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Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems Takashi YAMADA Shoji GOTO Norihisa TAKAYAMA Yoshifumi MATSUSHITA Yasoo HARADA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/01/01 Vol. E86-C No. 1 pp. 79-88 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: matched filter, spread-spectrum, WCDMA, VLSI, low power,
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A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling Keiichi KUROKAWA Takuya YASUI Yoichi MATSUMURA Masahiko TOYONAGA Atsushi TAKAHASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2746-2755 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Clock Scheduling Keyword: clock scheduling, clock tree synthesis, high-speed, low power,
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A 3.2-mA 6-Bit Pipelined A/D Coverter for a Bluetooth RF Transceiver Tatsuji MATSUURA Junya KUDOH Eiki IMAIZUMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/08/01 Vol. E85-C No. 8 pp. 1538-1545 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance Analog Integrated Circuits) Category: Keyword: A/D converter, CMOS, low power, pipeline, Bluetooth,
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A 0.99 µA Operating Current Li-Ion Battery Protection IC Yen-Shyung SHYU Jiin-Chuan WU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/05/01 Vol. E85-C No. 5 pp. 1211-1215 Type of Manuscript: LETTER Category: Optoelectronics Keyword: Li-ion battery, protection IC, low power, bandgap voltage,
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Adaptive Bitwidth Compression for Low Power Video Memory Design Vasily MOSHNYAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 797-803 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: bit-compression, low power, video memory, adaptive technique,
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Development of a CMOS Data Recovery PLL for DVD-ROMx14 Shiro DOSHO Naoshi YANAGISAWA Seiji WATANABE Takahiro BOKUI Kazuhiko NISHIKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/04/01 Vol. E85-A No. 4 pp. 764-769 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: DVD-ROM, data recovery, jitter detector, low power, frequency detector,
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Trends in High-Performance, Low-Power Cache Memory Architectures Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 304-314 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: High-Performance Technologies Keyword: cache, low power, high performance, microprocessor, survey,
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Wide-Input Range Linear Voltage-to-Current Converter Using Equivalent MOSFETs without Cutoff Region Kazuyuki WADA Shigetaka TAKAGI Nobuo FUJII
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/02/01 Vol. E85-A No. 2 pp. 347-353 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: voltage-to-current converter, low voltage, input range, low power, equivalent MOSFET,
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A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications Tetsuya YAMADA Makoto ISHIKAWA Yuji OGATA Takanobu TSUNODA Takahiro IRITA Saneaki TAMAKI Kunihiko NISHIYAMA Tatsuya KAMEI Ken TATEZAWA Fumio ARAKAWA Takuichiro NAKAZAWA Toshihiro HATTORI Kunio UCHIYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 253-262 Type of Manuscript: INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Keyword: embedded processor, low power, RISC, DSP, MAC,
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A Controller LSI for Realizing V_DD-Hopping Scheme with Off-the-Shelf Processors and Its Application to MPEG4 System Hiroshi KAWAGUCHI Gang ZHANG Seongsoo LEE Youngsoo SHIN Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 263-271 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: low power, real-time embedded system, dynamic voltage scaling, application slicing, MPEG4,
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Issue Queue Energy Reduction through Dynamic Voltage Scaling Vasily G. MOSHNYAGA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 272-278 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: issue queue, computer architecture, low power, voltage scaling,
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Omitting Cache Look-up for High-Performance, Low-Power Microprocessors Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 279-287 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: cache, low power, look up, run time,
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SIMD ISA Extensions: Power Efficiency on Multimedia on a Superscalar Processor Julien SEBOT Nathalie DRACH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 297-303 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Low-Power Technologies Keyword: multimedia, SIMD, superscalar, low power,
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Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design Sungjae KIM Hyungwoo LEE Juho KIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/01/01 Vol. E85-A No. 1 pp. 234-240 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: low power, glitch, gate sizing, buffer insertion,
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Motion Estimation Using Edge Enhanced Low-Bit Images for Lowpower MPEG Encoder Ayuko TAKAGI Kiyoshi NISHIKAWA Hitoshi KIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 pp. 1900-1908 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Image/Visual Signal Processing Keyword: low power, motion estimation, MPEG, low-bit image, edge enhancement,
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Selective Clock Suppression of Protocol Modules for a Low Power Protocol Converter Young Moo LEE Kyu Ho PARK
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/07/01 Vol. E84-D No. 7 pp. 906-909 Type of Manuscript: LETTER Category: Computer System Element Keyword: CMOS digital integrated circuit, low power, protocol conversion,
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Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/03/01 Vol. E84-C No. 3 pp. 399-409 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: motion estimation, low bit resolution, VLSI architecture, parallelism, low power,
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Dynamic Floating Body Control SOI CMOS for Power Managed Multimedia ULSIs Fukashi MORISHITA Kazutami ARIMOTO Kazuyasu FUJISHIMA Hideyuki OZAKI Tsutomu YOSHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 253-259 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SOI, floating body, body control, high speed, low power,
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A Low Power Media Processor Core Performable CIF30 fr/s MPEG4/H26x Video Codec Hideo OHIRA Toshihisa KAMEMARU Hirokazu SUZUKI Ken-ichi ASANO Masahiko YOSHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 157-165 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: VLSI, media processor core, video coding, low power, high performance,
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Random Modulation: Multi-Threshold-Voltage Design Methodology in Sub-2-V Power Supply CMOS Naoki KATO Yohei AKITA Mitsuru HIRAKI Takeo YAMASHITA Teruhisa SHIMIZU Fuyuhiko MAKI Kazuo YANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/20 Vol. E83-C No. 11 pp. 1747-1754 Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: CMOS, threshold voltage, leakage current, low power,
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A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size Koji INOUE Koji KAI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/11/20 Vol. E83-C No. 11 pp. 1716-1723 Type of Manuscript: Special Section PAPER (Special Issue on Low-power LSIs and Technologies) Category: Keyword: cache, low power, variable line-size, merged DRAM/logic LSIs, high bandwidth,
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A 3 V Low Power 156/622/1244 Mbps CMOS Parallel Clock and Data Recovery Circuit for Optical Communications Hae-Moon SEO Chang-Gene WOO Sang-Won OH Sung-Wook JUNG Pyung CHOI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/08/20 Vol. E83-A No. 8 pp. 1720-1727 Type of Manuscript: PAPER Category: General Fundamentals and Boundaries Keyword: parallel clock and data recovery, CMOS, optical communications, low power,
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Motion Estimation with Power Scalability and Its VHDL Model Ayuko TAKAGI Shogo MURAMATSU Hitoshi KIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/08/20 Vol. E83-A No. 8 pp. 1608-1613 Type of Manuscript: Special Section PAPER (Special Section on Digital Signal Processing) Category: Implementations of Signal Processing Systems Keyword: low power, motion estimation, MPEG, less gray level image,
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Low Power and Low Voltage MOSFETs with Variable Threshold Voltage Controlled by Back-Bias Toshiro HIRAMOTO Makoto TAKAMIYA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/20 Vol. E83-C No. 2 pp. 161-169 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: MOSFET, low power, low voltage, variable threshold voltage, back-bias, body effect, DTMOS, SOI,
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Approaches for Reducing Power Consumption in VLSI Bus Circuits Kunihiro ASADA Makoto IKEDA Satoshi KOMATSU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/20 Vol. E83-C No. 2 pp. 153-160 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: low power, reduced signal swing, signal transition reduction, bus encoding/decoding, time-domain circuit, minimum Hamming-distance detector,
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A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/20 Vol. E83-C No. 2 pp. 186-194 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: cache, low power, low energy, way prediction, high performance,
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A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/01/20 Vol. E83-C No. 1 pp. 109-114 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: cache, SRAM, low power, two-port, microprocessor,
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A High-Speed, Low-Power Phase Frequency Detector and Charge-Pump Circuits for High Frequency Phase-Locked Loops Won-Hyo LEE Sung-Dae LEE Jun-Dong CHO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/20 Vol. E82-A No. 11 pp. 2514-2520 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: PFD, charge-pump, low power, PLL, high speed, D flip-flop, error detection range,
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Low-Power Scheme of NMOS 4-Phase Dynamic Logic Bao-Yu SONG Makoto FURUIE Yukihiro YOSHIDA Takao ONOYE Isao SHIRAKAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1772-1776 Type of Manuscript: Special Section LETTER (Special Issue on Integrated Electronics and New System Paradigms) Category: Low-Power Circuit Technique Keyword: low power, 4-phase dynamic logic, short-circuit current, small voltage swing,
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A Low-Power Half-Swing Clocking Scheme for Flip-Flop with Complementary Gate and Source Drive Jin-Cheon KIM Sang-Hoon LEE Hong-June PARK
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1777-1779 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: CMOS flip-flop, low power, half-swing clocking, complementary drive,
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A 1-V, 1-V_p-p Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors Koichi TANNO Okihiko ISHIZUKA Zheng TANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/05/20 Vol. E82-C No. 5 pp. 750-757 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: multiplier, low voltage, low power, neuron MOS transistor, analog integrated circuit,
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Analysis and Optimization of Floating Body Cell Operation for High-Speed SOI-DRAM Fukashi MORISHITA Yasuo YAMAGUCHI Takahisa EIMORI Toshiyuki OASHI Kazutami ARIMOTO Yasuo INOUE Tadashi NISHIMURA Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/20 Vol. E82-C No. 3 pp. 544-552 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Silicon Devices Keyword: SOI-DRAM, floating body, high speed, low power, data retention characteristics,
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High Frequency Characteristics of Dynamic Threshold-Voltage MOSFET (DTMOS) under Ultra-Low Supply Voltage Tetsu TANAKA Youichi MOMIYAMA Toshihiro SUGII
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/20 Vol. E82-C No. 3 pp. 538-543 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Silicon Devices Keyword: SOI, DTMOS, F_t, F_max, low power,
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A Flip-Flop Circuit with a Directly Controlled Emitter-Follower and a Level Stabilizer for Low-Power Prescalers Hisayasu SATO Nagisa SASAKI Takahiro MIKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/03/20 Vol. E82-C No. 3 pp. 504-510 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed IC and LSI Technology) Category: Silicon Devices Keyword: prescaler, flip-flop, emitter-follower, low power,
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Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture Nobutaro SHIBATA Hiroshi INOKAWA Keiichiro TOKUNAGA Soichi OHTA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/01/20 Vol. E82-C No. 1 pp. 94-104 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, macrocell, size-configurable, high speed, low power, per-bitline architecture, current-sense amplifier, squashed memory cell, trench isolation,
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Instruction Scheduling to Reduce Switching Activity of Off-Chip Buses for Low-Power Systems with Caches Hiroyuki TOMIYAMA Tohru ISHIHARA Akihiko INOUE Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/20 Vol. E81-A No. 12 pp. 2621-2629 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Compiler Keyword: compiler optimization, instruction scheduling, low power, caches,
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Three Dimensional Image Analysis of Multi-Field Driving Method for Reducing Multi-Media LCD Power Consumption Haruhiko OKUMURA Goh ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/11/20 Vol. E81-C No. 11 pp. 1691-1696 Type of Manuscript: Special Section PAPER (Special Issue on Electronic Displays) Category: Keyword: driving method, multi-media, low power, TFT-LCD,
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Design of Low Power Digital VLSI Circuits Based on a Novel Pass-Transistor Logic Minkyu SONG Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/11/20 Vol. E81-C No. 11 pp. 1740-1749 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: power saved pass-transistor logic (PSPL), low power, regenerative feedback, 5454-bit multiplier, 7-bit serial counter,
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Ultra-Low Power Two-MOS Virtual-Short Circuit and Its Application Koichi TANNO Okihiko ISHIZUKA Zheng TANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/10/20 Vol. E81-A No. 10 pp. 2194-2200 Type of Manuscript: PAPER Category: Analog Signal Processing Keyword: virtual-short, weak-inversion region, low power, low voltage, CMOS analog circuit, integrated circuit,
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Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs Taku OHSAWA Koji KAI Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/20 Vol. E81-C No. 9 pp. 1455-1462 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: DRAM, DRAM refresh, merged DRAM/logic, system LSI, low power,
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A Fast Frequency Switching Synthesizer with a Digitally Controlled Delay Generator Hideyuki NOSAKA Tadao NAKAGAWA Akihiro YAMAGISHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/07/20 Vol. E81-A No. 7 pp. 1466-1472 Type of Manuscript: Special Section PAPER (Special Section on Fundamentals of Multi-dimensional Mobile Information Network) Category: Keyword: direct digital synthesizer, frequency synthesizer, low power, spread spectrum, frequency hopping, spurious signals,
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Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/20 Vol. E81-C No. 5 pp. 759-767 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: integration of DRAM and logic, embedded DRAM, low power, high memory bandwidth,
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An LSI for Low Bit-Rate Image Compression Using Vector Quantization Kazutoshi KOBAYASHI Noritsugu NAKAMURA Kazuhiko TERADA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/20 Vol. E81-C No. 5 pp. 718-724 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: parallel processor, memory-based, vector quantization, low bit-rate image compression, low power, SIMD,
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Bipartition and Synthesis in Low Power Pipelined Circuits Shyh-Jong CHEN Rung-Ji SHANG Xian-June HUANG Shang-Jang RUAN Feipei LAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/04/20 Vol. E81-A No. 4 pp. 664-671 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: bipartition, synthesis, low power, gated-clock, pipelined circuit,
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Low Power Management Method for PDS ONU Logic LSIs Koichi SAITO Kiyoshi MATSUMOTO Kennosuke FUKAMI
Publication: IEICE TRANSACTIONS on Communications Publication Date: 1998/03/20 Vol. E81-B No. 3 pp. 604-608 Type of Manuscript: PAPER Category: Communication Device and Circuit Keyword: LSI, logic LSI, low power, PDS, ONU,
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10 µA Quiescent Current Opamp Design for LCD Driver ICs Tetsuro ITAKURA Hironori MINAMIZAKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/02/20 Vol. E81-A No. 2 pp. 230-236 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques in the Digital-Oriented Era) Category: Keyword: analog circuits and signal processing, integrated electronics, CMOS opamp, low power,
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A Switched Virtual-GND Level Technique for Fast and Low Power SRAM's Nobutaro SHIBATA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1598-1607 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: SRAM, low power, virtual GND, column address, synchronous, macrocell,
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Low-Power Circuit Design Techniques for Si Bipolar Gbit/s LSIsAn Overview Haruhiko ICHINO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1511-1522 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: Si bipolar, high speed, low power, optical transmission,
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Design and Architecture for Low-Power/High-Speed RISC Microprocessor: SuperH Hideo MAEJIMA Masahiro KAINAGA Kunio UCHIYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1539-1545 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: RISC, architecture, low power, high speed, microprocessor,
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A 100 MIPS High Speed and Low Power Digital Signal Processor Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuji OZAWA Kenichi TASHIRO Shigetoshi MURAMATSU Masahiro FUSUMADA Akemi TODOROKI Youichi TANAKA Masayasu ITOIGAWA Isao MORIOKA Hiroyuki MIZUNO Miki KOJIMA Giovanni NASO Emmanuel EGO Frank CHIRAT
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1546-1552 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: 100 MIPS, digital signal processing, high speed, low power, CPU,
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Low Power Neuron-MOS Technology for High-Functionality Logic Gate Synthesis Ho-Yup KWON Koji KOTANI Tadashi SHIBATA Tadahiro OHMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/07/20 Vol. E80-C No. 7 pp. 924-930 Type of Manuscript: Special Section PAPER (Special Issue on New Concept Device and Novel Architecture LSIs) Category: Novel Concept Devices Keyword: neuron MOS, deep-threshold, low power, full adder, number detector,
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A Low Power 622MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD Hiroyasu YOSHIZAWA Kenji TANIGUCHI Hiroyuki SHIRAHAMA Kenichi NAKASHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/06/20 Vol. E80-A No. 6 pp. 1015-1020 Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1996 International Technical Conference on Circuits/Systems, Computers and Communications(ITC-CSCC'96)) Category: Keyword: PLL, PFD, VCO, low power, source coupling, dynamic circuit,
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The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications Yuichi KADO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/03/20 Vol. E80-C No. 3 pp. 443-454 Type of Manuscript: INVITED PAPER (Special Issue on SOI Devices and Their Process Technologies) Category: Circuit Technologies and Applications Keyword: CMOS, SOI, SIMOX, low voltage, low power,
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Design of a Low-Voltage, Low-Power, High-Frequency CMOS Current-Mode VCO Circuit by Using 0.6µm MOS Devices Yasuhiro SUGIMOTO Takeshi UENO Takaaki TSUJI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/02/20 Vol. E80-A No. 2 pp. 304-312 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques for System-on-Chip Integration) Category: Keyword: CMOS VCO, current-mode circuit, low voltage, low power, high-frequency,
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An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors Yasuhisa SHIMAZAKI Katsuhiro NORISUE Koichiro ISHIBASHI Hideo MAEJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/20 Vol. E79-C No. 12 pp. 1693-1698 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: RISC microprocessor, cache memory, low power,
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Low Power Multi-Media TFT-LCD Using Multi-Field Driving Method Haruhiko OKUMURA Goh ITOH Kouhei SUZUKI Kouji SUZUKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/08/20 Vol. E79-C No. 8 pp. 1109-1111 Type of Manuscript: Special Section LETTER (Special Issue on Liquid-Crystal Displays) Category: Keyword: driving method, multi-media, low power, TFT-LCD, interlace scan,
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A 5-mW, 10-ns Cycle TLB Using a High-Performance CAM with Low-Power Match-Detection Circuits Hisayuki HIGUCHI Suguru TACHIBANA Masataka MINAMI Takahiro NAGANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/06/20 Vol. E79-C No. 6 pp. 757-762 Type of Manuscript: Special Section PAPER (Special Issue on ULSI Memory Technology) Category: Static RAMs Keyword: TLB, CAM, low power, fully associative,
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A 1.3 V Supply Voltage AlGaAs/InGaAs HJFET SCFL D-FF Operating at up to 10 Gbps Masahiro FUJII Tadashi MAEDA Yasuo OHNO Masatoshi TOKUSHIMA Masaoki ISHIKAWA Muneo FUKAISHI Hikaru HIDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/20 Vol. E79-C No. 4 pp. 512-517 Type of Manuscript: Special Section PAPER (Special Issue on Ultra-High-Speed LSIs) Category: Keyword: low power, high speed, GaAs, heterojunction FET, SCFL, logic swing, low supply voltage, D-FF,
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Partitioned-Bus and Variable-Width-Bus Scheme for Low Power Digital Processors Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/03/20 Vol. E79-C No. 3 pp. 424-429 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: low power, partitioned-bus architecture, variable-width-bus scheme, microprocessor,
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A Current-Mode Bit-Block Circuit Applicable to Low-Voltage, Low-Power Pipeline Video-Speed A/D Converters Yasuhiro SUGIMOTO Shunsaku TOKITO Hisao KAKITANI Eitaro SETA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/02/20 Vol. E79-A No. 2 pp. 199-209 Type of Manuscript: Special Section PAPER (Special Section on Analog Technologies in Submicron Era) Category: Keyword: ADC bit-block circuit, current-mode circuit, pipeline-type ADC, video-speed ADC, low voltage, low power,
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A Low-Power and High-Speed Impulse-Transmission CMOS Interface Circuit Masafumi NOGAWA Yusuke OHTOMO Masayuki INO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/12/20 Vol. E78-C No. 12 pp. 1733-1737 Type of Manuscript: Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: CMOS, low-voltage swing, interface, low power, high speed, impulse transmission,
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Low-power LSI Circuit Technologies for Portable Terminal Equipment Shoji HORIGUCHI Tsuneo TSUKAHARA Hideki FUKUDA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/12/20 Vol. E78-C No. 12 pp. 1655-1667 Type of Manuscript: INVITED PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: low voltage, low power, portable terminal equipment, multi-threshold CMOS,
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A Circuit Library for Low Power and High Speed Digital Signal Processor Hiroshi TAKAHASHI Shigeshi ABIKO Shintaro MIZUSHIMA Yuni OZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/12/20 Vol. E78-C No. 12 pp. 1717-1725 Type of Manuscript: Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia) Category: Keyword: low power, high speed, low cost, GSM, PDC, NADC, digital signal processing, personal communication, 50 MIPS, CPU,
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Data Bypassing Register File for Low Power Microprocessor Makoto IKEDA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/10/20 Vol. E78-C No. 10 pp. 1470-1472 Type of Manuscript: LETTER Category: Integrated Electronics Keyword: low power, data bypassing register file, microprocessor, implicit data bypassing scheme,
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High Speed GaAs Digital Integrated Circuits Masahiro AKIYAMA Seiji NISHI Yasushi KAWAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/09/20 Vol. E78-C No. 9 pp. 1165-1170 Type of Manuscript: INVITED PAPER (Special Issue on Ultra-High-Speed Electron Devices) Category: Keyword: GaAs digital IC, DCFL, SBFL, high speed, low power, self-alignment process, recessed gate process, circuit design, standard cell,
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A Low-Power Synchronous SRAM Macrocell with Latch-Type Fast Sense Circuits Nobutaro SHIBATA Mayumi WATANABE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/07/20 Vol. E78-C No. 7 pp. 797-804 Type of Manuscript: Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age) Category: Keyword: marcocell, memory, synchronous, low power, latch type,
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Synergistic Power/Area Optimization with Transistor Sizing and Wire Length Minimization Masaaki YAMADA Sachiko KUROSAWA Reiko NOJIMA Naohito KOJIMA Takashi MITSUHASHI Nobuyuki GOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1995/04/20 Vol. E78-C No. 4 pp. 441-446 Type of Manuscript: Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits) Category: DA/Architecture Keyword: LSI, layout, transistor sizing, low power, CAD,
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An MOS Current Mode Logic (MCML) Circuit for Low-Power Sub-GHz Processors Masakazu YAMASHINA Hachiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1992/10/20 Vol. E75-C No. 10 pp. 1181-1187 Type of Manuscript: Special Section PAPER (Special Issue on Microprocessors) Category: Low-Voltage Operation Keyword: current mode logic, low power, high speed, MOS,
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