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Keyword : low power design

A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks Meng XU Xincun JI Jianhui WU Meng ZHANG
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2013/04/01 Vol. E96-B No. 4 pp. 939-947 Type of Manuscript: PAPER Category: Fundamental Theories for Communications Keyword: LDPC, Multimedia Wireless Sensor Networks, low power design, layered decoding, memory bypassing scheme, Benes network,
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Energy-Aware Task Scheduling for Real-Time Systems with Discrete Frequencies Dejun QIAN Zhe ZHANG Chen HU Xincun JI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2011/04/01 Vol. E94-D No. 4 pp. 822-832 Type of Manuscript: PAPER Category: Software System Keyword: real-time system, low power design, dynamic voltage scaling, stochastic speed scheduling,
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Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g_m/I_D Lookup Table Methodology Takayuki KONISHI Kenji INAZU Jun Gyu LEE Masanori NATSUI Shoichi MASUI Boris MURMANN
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/03/01 Vol. E94-C No. 3 pp. 334-345 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: operational transconductance amplifier, design optimization, analog design methodology, low power design,
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Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming Ki-Yong AHN Chong-Min KYUNG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/09/01 Vol. E92-A No. 9 pp. 2318-2325 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: system on chip, low power design, partitioning, integer linear programming,
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Design of Low Power QPP Interleave Address Generator Using the Periodicity of QPP Won-Ho LEE Chong Suck RIM
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-A No. 6 pp. 1538-1540 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: QPP, interleaver, low power design, turbo decoder, address generator,
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Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters Sergio SAPONARA Pierluigi NUZZO Claudio NANI Geert VAN DER PLAS Luca FANUCCI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/06/01 Vol. E92-C No. 6 pp. 843-851 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies) Category: Keyword: A/D converters, time interleaving, analog CMOS circuits, system level design, SAR, low power design,
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A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost Tsung-Yi WU Jr-Luen TZENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2718-2726 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Circuit Synthesis Keyword: leakage current reduction, minimum leakage vector, minimum leakage vector controller, low power design,
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Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM Masaaki IIJIMA Kayoko SETO Masahiro NUMA Akira TADA Takashi IPPOSHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2691-2694 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Memory Design and Test Keyword: PD-SOI, body-bias, SRAM, low power design,
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Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders Hiroaki SUZUKI Woopyo JEONG Kaushik ROY
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 865-876 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: adaptive supply voltage, low power design, adders, CMOS digital integrated circuit,
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Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation Masaaki IIJIMA Masayuki KITAMURA Masahiro NUMA Akira TADA Takashi IPPOSHI Shigeto MAEGAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 666-674 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Digital Keyword: low power design, PD-SOI, body-bias, pass-transistor logic, circuit simulation, SRAM,
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An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors CheolHong KIM SungWoo CHUNG ChuShik JHON
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/04/01 Vol. E89-D No. 4 pp. 1450-1458 Type of Manuscript: PAPER Category: Computer Systems Keyword: instruction cache, partitioned cache, low power design, dynamic energy, embedded processor,
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A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory Shoichi MASUI Toshiyuki TERAMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 601-607 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: INVITED Keyword: radio frequency identification, wireless communication, nonvolatile memory, ferroelectric random access memory, low power design,
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Bitwidth Optimization for Low Power Digital FIR Filter Design Kosuke TARUMI Akihiko HYODO Masanori MUROYAMA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 869-875 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: low power design, bitwidth optimization, digital FIR filter,
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Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation Takahiro KAKIMOTO Hiroyuki OCHI Takao TSUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2795-2798 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Keyword: low power design, wire length, floorplan, bit slice, one-hot code,
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An Efficient Nonlinear Charge Pump Cell for LCD Driver Min JIANG Bing YANG Lijiu JI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/11/01 Vol. E85-C No. 11 pp. 1844-1848 Type of Manuscript: Special Section PAPER (Special Issue on Electronic Displays) Category: Active Matrix Displays Keyword: low power design, charge pump circuit, LCD driver,
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Data Driven Power Saving for DCT/IDCT VLSI Macrocell Luca FANUCCI Sergio SAPONARA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/07/01 Vol. E85-A No. 7 pp. 1760-1765 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: very large scale integration architectures, low power design, design reuse, clock gating, video coding,
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Potential of Constructive Timing-Violation Toshinori SATO Itsujiro ARITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 323-330 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: High-Performance Technologies Keyword: instruction level parallelism, low power design, fault tolerance, timing constraints, speculative execution,
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Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2769-2777 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: transistor sizing, low power design, cell-base design, post-layout optimization, gate sizing,
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A System Level Optimization Technique for Application Specific Low Power Memories Tohru ISHIHARA Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2755-2761 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Optimization of Power and Timing Keyword: low power design, hardware/software codesign, memory, low voltage, embedded system,
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Trends in High-Performance, Low-Power Processor Architectures Kazuaki MURAKAMI Hidetaka MAGOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/02/01 Vol. E84-C No. 2 pp. 131-138 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies) Category: Keyword: processor architecture, high performance design, low power design,
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System LSI Design Methods for Low Power LSIs Hiroto YASUURA Tohru ISHIHARA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2000/02/20 Vol. E83-C No. 2 pp. 143-152 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies) Category: Keyword: low power design, system level, optimization, hardware/software codesign,
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A Memory Power Optimization Technique for Application Specific Embedded Systems Tohru ISHIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/20 Vol. E82-A No. 11 pp. 2366-2374 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: low power design, hardware/software codesign, memory, embedded system,
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A Low-Power A/D Conversion Technique Using Correlation of Moving Pictures Shoji KAWAHITO Junichi NAKA Yoshiaki TADOKORO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1764-1771 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Imaging Circuits and Algorithms Keyword: A/D converter, low power design, CMOS image sensor, moving picture correlation,
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On Sensor Motion Vector Estimation with Iterative Block Matching and Non-Destructive Image Sensing Dwi HANDOKO Shoji KAWAHITO Yoshiaki TADOKORO Akira MATSUZAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/20 Vol. E82-C No. 9 pp. 1755-1763 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Imaging Circuits and Algorithms Keyword: motion vector estimation, CMOS image sensor, non-destructive image sensing, low power design,
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Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier Daisuke MIYAZAKI Shoji KAWAHITO Yoshiaki TADOKORO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/02/20 Vol. E82-A No. 2 pp. 293-300 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: pipelined A/D converter, single-ended amplifier, low power design, portable video device,
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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay Hiroaki UEDA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/01/20 Vol. E82-D No. 1 pp. 301-308 Type of Manuscript: PAPER Category: Computer Systems Keyword: CMOS circuit, low power design, gate delay, transition probability, switching activity,
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Programmable Power Management Architecture for Power Reduction Tohru ISHIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/09/20 Vol. E81-C No. 9 pp. 1473-1480 Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures) Category: Keyword: low power design, power management, CMOS VLSI processor,
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A New Description of MOS Circuits at Switch-Level with Applications Massoud PEDRAM Xunwei WU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1892-1901 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: MOS, LSI, pass-transistor logic, switching theory, low power design,
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Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits Tohru ISHIHARA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/20 Vol. E80-A No. 3 pp. 480-486 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: CMOS VLSI circuits, low power design, power estimation,
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Experiments with Power Optimization in Gate Sizing Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1994/11/20 Vol. E77-A No. 11 pp. 1913-1916 Type of Manuscript: Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference) Category: Keyword: low power design, power dissipation, gate sizing, area–power–delay tradeoff,
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