Keyword : low power design


Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach
Carlos Cesar CORTES TORRES Hayate OKUHARA Nobuyuki YAMASAKI Hideharu AMANO 
Publication:   
Publication Date: 2018/04/01
Vol. E101-D  No. 4 ; pp. 1116-1125
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
silicon-on-insulatorSOTBbody biaslow power designtime-overheadenergy-overhead
 Summary | Full Text:PDF(1.4MB)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode
Koichiro ISHIBASHI Nobuyuki SUGII Shiro KAMOHARA Kimiyoshi USAMI Hideharu AMANO Kazutoshi KOBAYASHI Cong-Kha PHAM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2015/07/01
Vol. E98-C  No. 7 ; pp. 536-543
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power and High-Speed Chips)
Category: 
Keyword: 
microprocessorlow power design
 Summary | Full Text:PDF(2.2MB)

Low-Power Motion Estimation Processor with 3D Stacked Memory
Shuping ZHANG Jinjia ZHOU Dajiang ZHOU Shinji KIMURA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1431-1441
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
3DIC designmotion estimation processorlow power designmemory stacking
 Summary | Full Text:PDF(4.1MB)

A Low-Power LDPC Decoder for Multimedia Wireless Sensor Networks
Meng XU Xincun JI Jianhui WU Meng ZHANG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/04/01
Vol. E96-B  No. 4 ; pp. 939-947
Type of Manuscript:  PAPER
Category: Fundamental Theories for Communications
Keyword: 
LDPCMultimedia Wireless Sensor Networkslow power designlayered decodingmemory bypassing schemeBenes network
 Summary | Full Text:PDF(3MB)

Energy-Aware Task Scheduling for Real-Time Systems with Discrete Frequencies
Dejun QIAN Zhe ZHANG Chen HU Xincun JI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/04/01
Vol. E94-D  No. 4 ; pp. 822-832
Type of Manuscript:  PAPER
Category: Software System
Keyword: 
real-time systemlow power designdynamic voltage scalingstochastic speed scheduling
 Summary | Full Text:PDF(381.2KB)

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology
Takayuki KONISHI Kenji INAZU Jun Gyu LEE Masanori NATSUI Shoichi MASUI Boris MURMANN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 334-345
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
operational transconductance amplifierdesign optimizationanalog design methodologylow power design
 Summary | Full Text:PDF(1.4MB)

Power Minimization for Dual- and Triple-Supply Digital Circuits via Integer Linear Programming
Ki-Yong AHN Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/09/01
Vol. E92-A  No. 9 ; pp. 2318-2325
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
system on chiplow power designpartitioninginteger linear programming
 Summary | Full Text:PDF(380.5KB)

Design of Low Power QPP Interleave Address Generator Using the Periodicity of QPP
Won-Ho LEE Chong Suck RIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1538-1540
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
QPPinterleaverlow power designturbo decoderaddress generator
 Summary | Full Text:PDF(160.5KB)

Architectural Exploration and Design of Time-Interleaved SAR Arrays for Low-Power and High Speed A/D Converters
Sergio SAPONARA Pierluigi NUZZO Claudio NANI Geert VAN DER PLAS Luca FANUCCI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/06/01
Vol. E92-C  No. 6 ; pp. 843-851
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
A/D converterstime interleavinganalog CMOS circuitssystem level designSARlow power design
 Summary | Full Text:PDF(921.8KB)

A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
Tsung-Yi WU Jr-Luen TZENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2718-2726
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
leakage current reductionminimum leakage vectorminimum leakage vector controllerlow power design
 Summary | Full Text:PDF(591.8KB)

Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM
Masaaki IIJIMA Kayoko SETO Masahiro NUMA Akira TADA Takashi IPPOSHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2691-2694
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Memory Design and Test
Keyword: 
PD-SOIbody-biasSRAMlow power design
 Summary | Full Text:PDF(354.2KB)

Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders
Hiroaki SUZUKI Woopyo JEONG Kaushik ROY 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 865-876
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
adaptive supply voltagelow power designaddersCMOS digital integrated circuit
 Summary | Full Text:PDF(1.5MB)

Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation
Masaaki IIJIMA Masayuki KITAMURA Masahiro NUMA Akira TADA Takashi IPPOSHI Shigeto MAEGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 666-674
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
low power designPD-SOIbody-biaspass-transistor logiccircuit simulationSRAM
 Summary | Full Text:PDF(862.2KB)

An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors
CheolHong KIM SungWoo CHUNG ChuShik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1450-1458
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
instruction cachepartitioned cachelow power designdynamic energyembedded processor
 Summary | Full Text:PDF(2.9MB)

A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory
Shoichi MASUI Toshiyuki TERAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 601-607
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
radio frequency identificationwireless communicationnonvolatile memoryferroelectric random access memorylow power design
 Summary | Full Text:PDF(898.6KB)

Bitwidth Optimization for Low Power Digital FIR Filter Design
Kosuke TARUMI Akihiko HYODO Masanori MUROYAMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 869-875
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low power designbitwidth optimizationdigital FIR filter
 Summary | Full Text:PDF(526.9KB)

Datapath-Layout-Driven Design for Low-Power Standard-Cell LSI Implementation
Takahiro KAKIMOTO Hiroyuki OCHI Takao TSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2795-2798
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
low power designwire lengthfloorplanbit sliceone-hot code
 Summary | Full Text:PDF(255KB)

An Efficient Nonlinear Charge Pump Cell for LCD Driver
Min JIANG Bing YANG Lijiu JI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/11/01
Vol. E85-C  No. 11 ; pp. 1844-1848
Type of Manuscript:  Special Section PAPER (Special Issue on Electronic Displays)
Category: Active Matrix Displays
Keyword: 
low power designcharge pump circuitLCD driver
 Summary | Full Text:PDF(637.3KB)

Data Driven Power Saving for DCT/IDCT VLSI Macrocell
Luca FANUCCI Sergio SAPONARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7 ; pp. 1760-1765
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
very large scale integration architectureslow power designdesign reuseclock gatingvideo coding
 Summary | Full Text:PDF(466.8KB)

Potential of Constructive Timing-Violation
Toshinori SATO Itsujiro ARITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 323-330
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
instruction level parallelismlow power designfault tolerancetiming constraintsspeculative execution
 Summary | Full Text:PDF(353.2KB)

Post-Layout Transistor Sizing for Power Reduction in Cell-Base Design
Masanori HASHIMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2769-2777
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
transistor sizinglow power designcell-base designpost-layout optimizationgate sizing
 Summary | Full Text:PDF(806.1KB)

A System Level Optimization Technique for Application Specific Low Power Memories
Tohru ISHIHARA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2755-2761
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
low power designhardware/software codesignmemorylow voltageembedded system
 Summary | Full Text:PDF(557.2KB)

Trends in High-Performance, Low-Power Processor Architectures
Kazuaki MURAKAMI Hidetaka MAGOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 131-138
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
processor architecturehigh performance designlow power design
 Summary | Full Text:PDF(185.1KB)

System LSI Design Methods for Low Power LSIs
Hiroto YASUURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2 ; pp. 143-152
Type of Manuscript:  INVITED PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
low power designsystem leveloptimizationhardware/software codesign
 Summary | Full Text:PDF(801.9KB)

A Memory Power Optimization Technique for Application Specific Embedded Systems
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2366-2374
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
low power designhardware/software codesignmemoryembedded system
 Summary | Full Text:PDF(1.3MB)

A Low-Power A/D Conversion Technique Using Correlation of Moving Pictures
Shoji KAWAHITO Junichi NAKA Yoshiaki TADOKORO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1764-1771
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Imaging Circuits and Algorithms
Keyword: 
A/D converterlow power designCMOS image sensormoving picture correlation
 Summary | Full Text:PDF(1.9MB)

On Sensor Motion Vector Estimation with Iterative Block Matching and Non-Destructive Image Sensing
Dwi HANDOKO Shoji KAWAHITO Yoshiaki TADOKORO Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/09/25
Vol. E82-C  No. 9 ; pp. 1755-1763
Type of Manuscript:  Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms)
Category: Imaging Circuits and Algorithms
Keyword: 
motion vector estimationCMOS image sensornon-destructive image sensinglow power design
 Summary | Full Text:PDF(1.4MB)

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier
Daisuke MIYAZAKI Shoji KAWAHITO Yoshiaki TADOKORO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/02/25
Vol. E82-A  No. 2 ; pp. 293-300
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
pipelined A/D convertersingle-ended amplifierlow power designportable video device
 Summary | Full Text:PDF(858.2KB)

Power Estimation and Reduction of CMOS Circuits Considering Gate Delay
Hiroaki UEDA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/01/25
Vol. E82-D  No. 1 ; pp. 301-308
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
CMOS circuitlow power designgate delaytransition probabilityswitching activity
 Summary | Full Text:PDF(202.7KB)

Programmable Power Management Architecture for Power Reduction
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1473-1480
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
low power designpower managementCMOS VLSI processor
 Summary | Full Text:PDF(677.5KB)

A New Description of MOS Circuits at Switch-Level with Applications
Massoud PEDRAM Xunwei WU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1892-1901
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
MOSLSIpass-transistor logicswitching theorylow power design
 Summary | Full Text:PDF(744.1KB)

Experimental Analysis of Power Estimation Models of CMOS VLSI Circuits
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 480-486
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
CMOS VLSI circuitslow power designpower estimation
 Summary | Full Text:PDF(520.2KB)

Experiments with Power Optimization in Gate Sizing
Guangqiu CHEN Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1913-1916
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
low power designpower dissipationgate sizingarea–power–delay tradeoff
 Summary | Full Text:PDF(267.1KB)