Keyword : logic optimization


Super-Set of Permissible Functions and Its Application to the Transduction Method
Katsunori TANAKA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3124-3133
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic optimizationpermissible function (PF)transduction methodCSPFMSPFsuper-set of permissible functions (SSPF)
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Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2554-2562
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic optimizationFPGAsSPFDsPSPFDs
 Summary | Full Text:PDF(818.2KB)

Logic Optimization: Redundancy Addition and Removal Using Implication Relations
Hideyuki ICHIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 724-730
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword: 
logic optimizationimplicationredundancy identification
 Summary | Full Text:PDF(623.4KB)

Generating Random Benchmark Circuits with Restricted Fan-Ins
Kazuo IWAMA Kensuke HINO Hiroyuki KUROKAWA Sunao SAWADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/10/25
Vol. E80-D  No. 10 ; pp. 1009-1016
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Design
Keyword: 
logic optimizationbenchmark circuitsrandom benchmarking
 Summary | Full Text:PDF(702.4KB)

Network Hierarchies and Node Minimization
Robert K. BRAYTON Ellen M. SENTOVICH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 199-208
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Logic Synthesis
Keyword: 
logic synthesislogic optimizationdon't caresBoolean relationsnondeterministic finite automata
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Timing Optimization of Multi-Level Networks Using Boolean Relations
Yuji KUKIMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/03/25
Vol. E76-A  No. 3 ; pp. 362-369
Type of Manuscript:  Special Section PAPER (Special Section on the 5th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
timing optimizationlogic synthesislogic optimizationBoolean relationsBoolean unification
 Summary | Full Text:PDF(696.8KB)

Applications of Boolean Unification to Combinational Logic Synthesis
Yuji KUKIMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1212-1219
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Boolean unificationBoolean equationslogic synthesislogic optimizationBoolean relations
 Summary | Full Text:PDF(648.3KB)