Keyword : leakage power


Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis
Nan WANG Song CHEN Wei ZHONG Nan LIU Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/08/01
Vol. E97-A  No. 8 ; pp. 1709-1719
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
mobility overlap removaldual-Vthleakage powerregister usagehigh-level synthesis
 Summary | Full Text:PDF(1.9MB)

Leakage Power Aware Scheduling in High-Level Synthesis
Nan WANG Song CHEN Cong HAO Haoran ZHANG Takeshi YOSHIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/04/01
Vol. E97-A  No. 4 ; pp. 940-951
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
dual-Vthleakage powermax-flow min-cut
 Summary | Full Text:PDF(2MB)

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2301-2308
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
low-powercacheleakage power
 Summary | Full Text:PDF(1.6MB)

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs
Kan WANG Sheqin DONG Yuchun MA Yu WANG Xianlong HONG Jason CONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2490-2498
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
leakage powerTSVdelay-power-temperature dependence
 Summary | Full Text:PDF(2.7MB)

Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model
Seidai TAKEDA Kyundong KIM Hiroshi NAKAMURA Kimiyoshi USAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2499-2509
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword: 
power gatingMTCMOSdelayleakage power
 Summary | Full Text:PDF(2MB)

A Leakage Efficient Instruction TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/08/01
Vol. E94-D  No. 8 ; pp. 1565-1574
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage powerTLBembedded processor
 Summary | Full Text:PDF(1.3MB)

A Large “Read” and “Write” Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM
Tadayoshi ENOMOTO Nobuaki KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 530-538
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
SRAMleakage power“write” margin“read” margin
 Summary | Full Text:PDF(1.4MB)

A Leakage Efficient Data TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1 ; pp. 51-59
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage powerTLBembedded processor
 Summary | Full Text:PDF(921.7KB)

A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates
How-Rern LIN Wei-Hao CHIU Tsung-Yi WU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 386-390
Type of Manuscript:  Special Section PAPER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
leakage powerleakage tolerancehigh performancedomino logic
 Summary | Full Text:PDF(291.3KB)

On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature
Takashi SATO Junji ICHIMIYA Nobuto ONO Masanori HASHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3491-3499
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
thermal gradient simulationleakage powertemperature-dependent leakage powerpower calculationleakage model
 Summary | Full Text:PDF(1MB)

Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits
Naoaki OHKUBO Kimiyoshi USAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3482-3490
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Simulation and Verification
Keyword: 
MTCMOSselective-MTstatic timing analysisleakage powerdelay modeling
 Summary | Full Text:PDF(1.1MB)

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era
Kazutoshi KOBAYASHI Masao ARAMOTO Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 552-558
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
parallel processingVLIWSMTlow powernanometerleakage power
 Summary | Full Text:PDF(1.1MB)

Dynamic Sleep Control for Finite-State-Machines to Reduce Active Leakage Power
Kimiyoshi USAMI Hiroshi YOSHIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3116-3123
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
leakage powerscalingactive leakageburn-inMTCMOS
 Summary | Full Text:PDF(1.1MB)

Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems
Jin-Hyeok CHOI Yong-Ju KIM Jae-Kyung WEE Seongsoo LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 629-633
Type of Manuscript:  Special Section LETTER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
shutdownwake-uppipelined structurepower stabilityMTCMOScut-off switchleakage power
 Summary | Full Text:PDF(1.5MB)