IEICE SEARCH SYSTEM

Keyword : interconnect

TSV Geometrical Variations and Optimization Metric with Repeaters for 3D IC Hung Viet NGUYEN Myunghwan RYU Youngmin KIM
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2012/12/01 Vol. E95-C No. 12 pp. 1864-1871 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: 3D IC, TSV (Through Silicon Via), power, delay, optimization, interconnect, repeater,
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A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects Jongsun KIM Gyungsu BYUN M. Frank CHANG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/05/01 Vol. E94-C No. 5 pp. 854-857 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, communication, RF interconnect, wire line transceiver, VLSI,
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Impact of Self-Heating in Wire Interconnection on Timing Toshiki KANAMOTO Takaaki OKUMURA Katsuhiro FURUKAWA Hiroshi TAKAFUJI Atsushi KUROKAWA Koutaro HACHIYA Tsuyoshi SAKATA Masakazu TANAKA Hidenari NAKASHIMA Hiroo MASUDA Takashi SATO Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/03/01 Vol. E93-C No. 3 pp. 388-392 Type of Manuscript: BRIEF PAPER Category: Keyword: interconnect, delay variation, parasitic resistance, thermal, temperature, self-heat, SoC,
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Prediction of Self-Heating in Short Intra-Block Wires Ken-ichi SHINKAI Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/03/01 Vol. E93-A No. 3 pp. 583-594 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: self-heating, temperature, interconnect, local wire, process scaling,
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Proximity Coupled Interconnect Using Broadside Coupled Composite Right/Left-Handed Transmission Line Naobumi MICHISHITA Akiyoshi ABE Yoshihide YAMADA Anthony LAI Tatsuo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2009/09/01 Vol. E92-C No. 9 pp. 1150-1156 Type of Manuscript: Special Section PAPER (Special Section on Recent Progress in Microwave and Millimeter-Wave Technologies and Their Applications) Category: Keyword: interconnect, composite right/left-handed transmission line, zeroth order resonance, broadside coupling,
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Accurate Modeling Method for Cu Interconnect Kenta YAMADA Hiroshi KITAHARA Yoshihiko ASAI Hideo SAKAMOTO Norio OKADA Makoto YASUDA Noriaki ODA Michio SAKURAI Masayuki HIROI Toshiyuki TAKEWAKI Sadayuki OHNISHI Manabu IGUCHI Hiroyasu MINDA Mieko SUZUKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/06/01 Vol. E91-C No. 6 pp. 968-977 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: Cu, interconnect, cross-section, modeling,
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Statistical Corner Conditions of Interconnect Delay (Corner LPE Specifications) Kenta YAMADA Noriaki ODA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 562-570 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: statistical, corner conditions, interconnect, LPE, delay,
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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation Noriaki ODA Hironori IMURA Naoyoshi KAWAHARA Masayoshi TAGAMI Hiroyuki KUNISHIMA Shuji SONE Sadayuki OHNISHI Kenta YAMADA Yumi KAKUHARA Makoto SEKINE Yoshihiro HAYASHI Kazuyoshi UENO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/04/01 Vol. E90-C No. 4 pp. 848-855 Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies) Category: Device Keyword: copper, low-k, CMOS, interconnect, design, application,
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Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation Toshiki KANAMOTO Shigekiyo AKUTSU Tamiyo NAKABAYASHI Takahiro ICHINOMIYA Koutaro HACHIYA Atsushi KUROKAWA Hiroshi ISHIKAWA Sakae MUROMOTO Hiroyuki KOBAYASHI Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3666-3670 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: interconnect, delay variation, parasitic capacitance, SoC,
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Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design Toshiki KANAMOTO Tatsuhiko IKEDA Akira TSUCHIYA Hidetoshi ONODERA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3560-3568 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: substrate, interconnect, resistance, inductance, SoC,
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Carbon Nanotube Technologies for LSI via Interconnects Yuji AWANO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/11/01 Vol. E89-C No. 11 pp. 1499-1503 Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies) Category: INVITED Keyword: carbon nanotube, interconnect, CVD, nanotechnology,
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RF Passive Components Using Metal Line on Si CMOS Kazuya MASU Kenichi OKADA Hiroyuki ITO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 681-691 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: INVITED Keyword: Si CMOS, on-chip passive, interconnect, transmission line, inductor, variable inductor, reconfigurable RF circuit,
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MIMO Interconnects Order Reductions by Using the Multiple Point Adaptive-Order Rational Global Arnoldi Algorithm Chia-Chi CHU Ming-Hong LAI Wu-Shiung FENG
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 792-802 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: rational Arnoldi algorithm, global Arnoldi algorithms, model reductions, interconnect, Krylov subspace, MIMO,
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Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills Atsushi KUROKAWA Akira KASEBE Toshiki KANAMOTO Yun YANG Zhangcai HUANG Yasuaki INOUE Hiroo MASUDA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 847-855 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: dummy fill, capacitance extraction, capacitance formula, interconnect,
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Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays Atsushi KUROKAWA Hiroo MASUDA Junko FUJII Toshinori INOSHITA Akira KASEBE Zhangcai HUANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/04/01 Vol. E89-A No. 4 pp. 856-864 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: interconnect, worst-case delay, static timing analysis, process variation, capacitance extraction,
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Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model Hidenari NAKASHIMA Junpei INOUE Kenichi OKADA Kazuya MASU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3358-3366 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: interconnect, layout compaction, physical design, placement, core utilization,
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A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures Toshiki KANAMOTO Tetsuya WATANABE Mitsutoshi SHIROTA Masayuki TERAI Tatsuya KUNIKIYO Kiyoshi ISHIKAWA Yoshihide AJIOKA Yasutaka HORIBA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3463-3470 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Interconnect Keyword: SoC, interconnect, physical parameter, low-k, capacitance, resistance, layout parasitic extraction,
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Timing-Driven Placement Based on Path Topology Analysis Feng CHENG Junfa MAO Xiaochun LI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/08/01 Vol. E88-A No. 8 pp. 2227-2230 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: timing-driven placement, interconnect, delay, critical path,
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A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula Hideki SHIMA Toshimasa MATSUOKA Kenji TANIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/05/01 Vol. E88-C No. 5 pp. 824-828 Type of Manuscript: Special Section PAPER (Special Section on Microelectronic Test Structures) Category: Keyword: spiral inductors, interconnect, closed-form expression, inductance extraction, analytical technique,
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Error Estimations of Arnoldi-Based Interconnect Model-Order Reductions Chia-Chi CHU Herng-Jer LEE Wu-Shiung FENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/02/01 Vol. E88-A No. 2 pp. 533-537 Type of Manuscript: Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: interconnect, model reductions, Arnordi iterations, residual error,
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Investigations of Optimum Tier Architectures for ASICs Kan TAKEUCHI Kazumasa YANAGISAWA Kazuko SAKAMOTO Teruya TANAKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/11/01 Vol. E87-A No. 11 pp. 2983-2989 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: packing efficiency, interconnect, Rent's rule, ASICs,
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Efficient Routing of Board-Level Optical Clocks for Ultra High-Speed Systems Chung-Seok (Andy) SEO Abhijit CHATTERJEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2004/06/01 Vol. E87-A No. 6 pp. 1310-1317 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003)) Category: Keyword: clock, optical waveguide, interconnect, physical design, optimization,
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Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays Sadahiro TANI Yoshihiro UCHIDA Makoto FURUIE Shuji TSUKIYAMA BuYeol LEE Shuji NISHI Yasushi KUBOTA Isao SHIRAKAWA Shigeki IMAI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2923-2932 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, LCD, parasitic capacitance, signal integrity, circuit simulation,
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Representative Frequency for Interconnect R(f)L(f)C Extraction Akira TSUCHIYA Masanori HASHIMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 2942-2951 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Parasitics and Noise Keyword: interconnect, extraction, frequency-dependent,
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Routing Methodology for Minimizing Crosstalk in SoC Takashi YAMADA Atsushi SAKAI Yoshifumi MATSUSHITA Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/09/01 Vol. E86-A No. 9 pp. 2347-2356 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: SoC, signal integrity, crosstalk, interconnect, timing analysis,
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Superconnect Technology Takayasu SAKURAI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2001/12/01 Vol. E84-C No. 12 pp. 1709-1716 Type of Manuscript: INVITED PAPER (Special Issue on Integrated Systems with New Concepts) Category: Keyword: system-on-a-chip, system-in-a-package, superconnect, RC delay, interconnect,
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Innovative Packaging and Fabrication Concept for a 28 GHz Communication Front-End Wolfgang MENZEL Jurgen KASSNER Uhland GOEBEL
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/11/20 Vol. E82-C No. 11 pp. 2021-2028 Type of Manuscript: INVITED PAPER (Special Issue on High-Frequency/High-Speed Devices for Information and Communication Systems in the 21st Century) Category: RF Assembly Technology Keyword: packaging, interconnect, fabrication techniques, plastic injection molding, waveguide filters,
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A Design Hierarchy of IC Interconnects and Gate Patterns Shinji ODANAKA Akio MISAKA Kyoji YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/20 Vol. E82-C No. 6 pp. 948-954 Type of Manuscript: INVITED PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: TCAD, interconnect, OPC, gate pattern, design rule,
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Non-uniform Multi-Layer IC Interconnect Transmission Line Characterization for Fast Signal Transient Simulation of High-Speed/High-Density VLSI Circuits Woojin JIN Hanjong YOO Yungseon EO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/06/20 Vol. E82-C No. 6 pp. 955-966 Type of Manuscript: Special Section PAPER (Special Issue on TCAD for Semiconductor Industries) Category: Keyword: interconnect, substrate effect, shielding effect, signal integrity, signal delay, crosstalk noise,
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Ribbon-Wire Interconnect Using Parasitic Element Hajime IZUMI Hiroyuki ARAI Tatsuo ITOH
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/04/20 Vol. E82-C No. 4 pp. 662-664 Type of Manuscript: LETTER Category: Microwave and Millimeter Wave Technology Keyword: ribbon-wire bonding, interconnect, DC-break, parasitic element, electromagnetic coupling, FDTD method,
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Inlaid Cu Interconnects Employing Ti-Si-N Barrier Metal for ULSI Applications Tadashi IIJIMA Yoshiaki SHIMOOKA Kyoichi SUGURO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/04/20 Vol. E79-C No. 4 pp. 568-572 Type of Manuscript: PAPER Category: Semiconductor Materials and Devices Keyword: Cu, Ti-Si-N, barrier, interconnect,
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An Analytical Modeling of Three Primary Wiring Capacitance Components for Multi-Layer Interconnect Structure Susumu KUROSAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/12/20 Vol. E78-A No. 12 pp. 1793-1798 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: capacitance, modeling, interconnect, LSI, LPE,
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