Keyword : interconnect delays


A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation
Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/01/01
Vol. E96-A  No. 1 ; pp. 312-321
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high-level synthesisRDRthermal-awarehot spotsinterconnect delays
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