|
|
Keyword : high-level synthesis
|
|
|
|
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths
Keisuke INOUE
Mineo KANEKO
|
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A
No. 12
pp. 2330-2337
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword:
clock-skew,
ordered clocking,
high-level synthesis,
|
| |
Summary |
Full Text:PDF
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A Stepwise Refinement Synthesis of Digital Systems for Testability Enhancement
Taewhan KIM
Ki-Seok CHUNG
C. L. LIU
|
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/20
Vol. E82-A
No. 6
pp. 1070-1081
Type of Manuscript: PAPER
Category: VLSI Design Technology and CAD
Keyword:
high-level synthesis,
testability,
scheduling,
|
| |
Summary |
Full Text:PDF
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs
Vasily G. MOSHNYAGA
Keikichi TAMARU
|
Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/20
Vol. E79-D
No. 10
pp. 1389-1395
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword:
high-level synthesis,
ASIC design methodology,
|
| |
Summary |
Full Text:PDF
|
|
|
Reclocking Controllers for Minimum Execution Time
Pradip JHA
Sri PARAMESWARAN
Nikil DUTT
|
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/20
Vol. E78-A
No. 12
pp. 1715-1721
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
reclocking,
high-level synthesis,
design reuse,
|
| |
Summary |
Full Text:PDF
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
High-Level Modeling and Synthesis of Communicating Processes Using VHDL
Wayne WOLF
Richard MANNO
|
Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/20
Vol. E76-D
No. 9
pp. 1039-1046
Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Design
Keyword:
high-level synthesis,
VHDL,
control-dominated systems,
|
| |
Summary |
Full Text:PDF
|
|
|
|
|
|
Functional Design of a Special Purpose Processor Based on High Level Specification Description
Hironobu KITABATAKE
Katsuhiko SHIRAI
|
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/20
Vol. E75-A
No. 10
pp. 1182-1190
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
high-level synthesis,
ASIC design,
VHDL,
|
| |
Summary |
Full Text:PDF
|
|
|
New Trend and Future Issues of Hardware Description Language and High-Level Synthesis
Masaharu IMAI
|
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/03/20
Vol. E75-A
No. 3
pp. 307-313
Type of Manuscript: INVITED PAPER (Special Section on the 4th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
HDL,
high-level synthesis,
VHDL,
verilog HDL,
UDL/I,
PARTHENON,
SFL,
|
| |
Summary |
Full Text:PDF
|
|
|
|
