Keyword : high-level synthesis (HLS)


VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks
David ALEDO Benjamin CARRION SCHAFER Félix MORENO 
Publication:   
Publication Date: 2019/03/01
Vol. E102-D  No. 3 ; pp. 512-521
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
VHDLSystemChigh-level synthesis (HLS)artificial neural network (ANN)
 Summary | Full Text:PDF(616KB)

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs
Koichi FUJIWARA Kazushi KAWAMURA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1294-1310
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
interconnection delayclock skewhigh-level synthesis (HLS)FPGAfloorplan
 Summary | Full Text:PDF(2MB)

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs
Koichi FUJIWARA Kazushi KAWAMURA Shin-ya ABE Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/07/01
Vol. E98-A  No. 7 ; pp. 1392-1405
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesis (HLS)FPGAfloorplaninterconnection delayMUX
 Summary | Full Text:PDF(3.4MB)