Keyword : high-level design


An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging
Yeonbok LEE Takeshi MATSUMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/07/01
Vol. E94-A  No. 7 ; pp. 1519-1529
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
post-silicon debugginghigh-level designI/O sequence mapping
 Summary | Full Text:PDF(1.2MB)

Linking Register-Transfer and Physical Levels of Design
Fadi J. KURDAHI Daniel D. GAJSKI Champaka RAMACHANDRAN Viraphol CHAIYAKUL 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/09/25
Vol. E76-D  No. 9 ; pp. 991-1005
Type of Manuscript:  INVITED PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Design
Keyword: 
layoutareadelayestimationhigh-level design
 Summary | Full Text:PDF(1.2MB)