Keyword : high level synthesis


Fixed Point Data Type Modeling for High Level Synthesis
Benjamin CARRION SCHAFER Yusuke IGUCHI Wataru TAKAHASHI Shingo NAGATANI Kazutoshi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 361-368
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
fixed pointdata typeshigh level synthesisautomationmodeling
 Summary | Full Text:PDF(749.8KB)

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
Shanghua GAO Hiroaki YOSHIDA Kenshu SETO Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1464-1475
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
software pipelininginterconnect delayhigh level synthesisschedulingperformance
 Summary | Full Text:PDF(1MB)

Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis
Takayuki OBATA Mineo KANEKO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3585-3595
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high level synthesisRT datapathskewwiring delayscheduling
 Summary | Full Text:PDF(398.5KB)

A Hierarchical Cost Estimation Technique for High Level Synthesis
Mahmoud MERIBOUT Masato MOTOMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2 ; pp. 444-461
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high level synthesishardware cost estimationmultiplexer-based architecturebus-based architectureschedulingallocationpartitioning
 Summary | Full Text:PDF(2.5MB)

Hardware Algorithm Optimization Using Bach C
Kazuhisa OKADA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high level synthesisbehavioral synthesisC languageBach C
 Summary | Full Text:PDF(341.7KB)

Symbolic Scheduling Techniques
Ivan P. RADIVOJEVI Forrest BREWER 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 224-230
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: High-Level Synthesis
Keyword: 
high level synthesisschedulingcomputer-aided designbinary decision diagrams
 Summary | Full Text:PDF(635.5KB)

Throughput Optimization by Data Flow Graph Transformation
Katsumi HARASHIMA Miki YOSHIDA Hironori KOMI Kunio FUKUNAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1917-1921
Type of Manuscript:  Special Section LETTER (Special Section of Letters Selected from the 1994 IEICE Spring Conference)
Category: 
Keyword: 
high level synthesisdata path schedulingdata flow graphiteration boundgraph transformation
 Summary | Full Text:PDF(310.8KB)