IEICE SEARCH SYSTEM

Keyword : hardware/software partitioning

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System Kang ZHAO Jinian BIAN Sheqin DONG Yang SONG Satoshi GOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2456-2464 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Electronic Circuits and Systems Keyword: hardware/software partitioning, CAD algorithm, search space smoothing, MPSoC, ASIP,
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Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis Hideki KAWAZU Jumpei UCHIDA Yuichiro MIYAOKA Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/04/01 Vol. E88-A No. 4 pp. 876-884 Type of Manuscript: Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa) Category: Keyword: processor synthesis, packed SIMD type operation, hardware/software partitioning, hardware/software cosynthesis, sub-operation parallelism,
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A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions Nozomu TOGAWA Koichi TACHIKAKE Yuichiro MIYAOKA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-A No. 12 pp. 3218-3224 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Design Methodology Keyword: processor synthesis, packed SIMD type instruction, hardware/software partitioning, hardware/software cosynthesis, DSP processor,
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A Hardware/Software Cosynthesis System for Processor Cores with Content Addressable Memories Nozomu TOGAWA Takao TOTSUKA Tatsuhiko WAKUI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/05/01 Vol. E86-A No. 5 pp. 1082-1092 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: content addressable memory, functional memory, micro processor core, hardware/software cosynthesis, hardware/software partitioning,
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A New Hardware/Software Partitioning Algorithm for DSP Processor Cores with Two Types of Register Files Nozomu TOGAWA Takashi SAKURAI Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2802-2807 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Hardware/Software Codesign Keyword: hardware/software cosynthesis, hardware/software partitioning, digital signal processor (DSP), register file, hardware unit,
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A Hardware/Software Cosynthesis System for Digital Signal Processor Cores Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1999/11/20 Vol. E82-A No. 11 pp. 2325-2337 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware/software cosynthesis, hardware/software partitioning, processor core, digital signal processing,
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