Keyword : hardware description language

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language
Naofumi HOMMA  Yuki WATANABE  Takafumi AOKI  Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12  pp. 3500-3509
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
datapaths,  formal design,  arithmetic circuits,  hardware algorithms,  hardware description language,  module generator, 
  Summary |  Full Text:PDF (875.2KB)
Program Slicing on VHDL Descriptions and Its Evaluation
Shigeru ICHINOSE  Mizuho IWAIHARA  Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/20
Vol. E81-A  No. 12  pp. 2585-2594
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Reuse
Keyword: 
hardware description language,  VHDL,  program slicing,  design reuse,  component extraction, 
  Summary |  Full Text:PDF (856.8KB)
Plastic Cell Architecture: A Scalable Device Architecture for General-Purpose Reconfigurable Computing
Kouichi NAGAMI  Kiyoshi OGURI  Tsunemichi SHIOZAWA  Hideyuki ITO  Ryusuke KONISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/20
Vol. E81-C  No. 9  pp. 1431-1437
Type of Manuscript: Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
reconfigurable computing,  FPGAs,  object-oriented,  hardware description language,  cellular automata, 
  Summary |  Full Text:PDF (690.5KB)
Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
Satoshi YOKOTA  Hiroyuki KANBARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/20
Vol. E78-A  No. 12  pp. 1742-1748
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description language,  conformance test,  logic synthesis,  UDL/I, 
  Summary |  Full Text:PDF (621.2KB)
Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment
Hiroyuki KANBARA  Satoshi YOKOTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/20
Vol. E78-A  No. 12  pp. 1749-1754
Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description language,  test suites,  validation,  CAD, 
  Summary |  Full Text:PDF (434.5KB)
Test Synthesis from Behavioral Description Based on Data Transfer Analysis
Mitsuteru YUKISHITA  Kiyoshi OGURI  Tsukasa KAWAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/20
Vol. E78-D  No. 3  pp. 248-251
Type of Manuscript: Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
computer hardware and design,  hardware description language,  test synthesis,  SFL, 
  Summary |  Full Text:PDF (253.1KB)