Keyword : hardware description language


ArchHDL: A Novel Hardware RTL Modeling and High-Speed Simulation Environment
Shimpei SATO Ryohei KOBAYASHI Kenji KISE 
Publication:   
Publication Date: 2018/02/01
Vol. E101-D  No. 2 ; pp. 344-353
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Design Methodology and Platform
Keyword: 
hardware description languageRTL modelingRTL simulation
 Summary | Full Text:PDF(831.3KB)

Formal Design of Arithmetic Circuits Based on Arithmetic Description Language
Naofumi HOMMA Yuki WATANABE Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3500-3509
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
datapathsformal designarithmetic circuitshardware algorithmshardware description languagemodule generator
 Summary | Full Text:PDF(874.3KB)

Program Slicing on VHDL Descriptions and Its Evaluation
Shigeru ICHINOSE Mizuho IWAIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2585-2594
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Reuse
Keyword: 
hardware description languageVHDLprogram slicingdesign reusecomponent extraction
 Summary | Full Text:PDF(853.1KB)

Plastic Cell Architecture: A Scalable Device Architecture for General-Purpose Reconfigurable Computing
Kouichi NAGAMI Kiyoshi OGURI Tsunemichi SHIOZAWA Hideyuki ITO Ryusuke KONISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1431-1437
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
reconfigurable computingFPGAsobject-orientedhardware description languagecellular automata
 Summary | Full Text:PDF(687.8KB)

Conformance Test of a Logic Synthesis System to the Standard HDL UDL/I
Satoshi YOKOTA Hiroyuki KANBARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1742-1748
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description languageconformance testlogic synthesisUDL/I
 Summary | Full Text:PDF(621.1KB)

Validation of UDL/I Test Suites and UDL/I Simulation/Synthesis Environment
Hiroyuki KANBARA Satoshi YOKOTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1749-1754
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware description languagetest suitesvalidationCAD
 Summary | Full Text:PDF(434.3KB)

Test Synthesis from Behavioral Description Based on Data Transfer Analysis
Mitsuteru YUKISHITA Kiyoshi OGURI Tsukasa KAWAOKA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/03/25
Vol. E78-D  No. 3 ; pp. 248-251
Type of Manuscript:  Special Section LETTER (Special Issue on Synthesis and Verification of Hardware Design)
Category: 
Keyword: 
computer hardware and designhardware description languagetest synthesisSFL
 Summary | Full Text:PDF(252KB)