Keyword : global routing


Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing
Peng-Yang HUNG Ying-Shu LOU Yih-Lang LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/03/01
Vol. E92-A  No. 3 ; pp. 880-889
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
track routingshield insertiondetailed routingcrosstalk optimizationglobal routingVLSI layout optimization
 Summary | Full Text:PDF(1MB)

Timing-Driven Global Routing with Efficient Buffer Insertion
Jingyu XU Xianlong HONG Tong JING 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11 ; pp. 3188-3195
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI layoutglobal routingtiming-drivenbuffer insertionroutability
 Summary | Full Text:PDF(220.3KB)

Timing-Constrained Flexibility-Driven Routing Tree Construction
Jin-Tai YAN Yen-Hsiang CHEN Chia-Fang LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1360-1368
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Programmable Logic, VLSI, CAD and Layout
Keyword: 
global routingrouting flexibilitySteiner treetiming constraint
 Summary | Full Text:PDF(721.2KB)

A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design
Jingyu XU Xianlong HONG Tong JING Yici CAI Jun GU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3158-3167
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Place and Routing
Keyword: 
high performance designglobal routingtiming-drivencoupling effects
 Summary | Full Text:PDF(660.8KB)

A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout
Tetsushi KOIDE Shin'ichi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2476-2484
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Layout Optimization
Keyword: 
building block layoutglobal routingpin assignmenttiming constraintsimulated evolution
 Summary | Full Text:PDF(880.2KB)

An Efficient Timing-Driven Global Routing Method for Standard Cell Layout
Tetsushi KOIDE Takeshi SUZUKI Shin'ichi WAKABAYASHI Noriyoshi YOSHIDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/10/25
Vol. E79-D  No. 10 ; pp. 1410-1418
Type of Manuscript:  Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
Category: Lauout Synthesis
Keyword: 
standard cell layoutglobal routingtiming constraintsslack distribution0-1 integer linear programming
 Summary | Full Text:PDF(856.1KB)

A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm
Tadanao TSUBOTA Masahiro KAWAKITA Takahiro WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 345-352
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
branch-and-boundlayoutglobal routingchannel-intersection graphanalogLSICAD
 Summary | Full Text:PDF(636.8KB)

A Hybrid Hierarchical Global Router for Multi-Layer VLSI's
Masayuki HAYASHI Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 337-344
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
hybrid hierarchical routerglobal routingmulti-layer routingCADVLSI
 Summary | Full Text:PDF(709.6KB)

A Global Router Optimizing Timing and Area for High-Speed Bipolar LSIs
Ikuo HARADA Yuichiro TAKEI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2058-2066
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
global routingtiming driven layoutbipolar LSIdelay modelrouting graphcritical path
 Summary | Full Text:PDF(893.5KB)

Maple: A Simultaneous Technology Mapping, Placement, and Global Routing Algorithm for Field-Programmable Gate Arrays
Nozomu TOGAWA Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2028-2038
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
FPGAlook up tabletechnology mappinglayout designplacementglobal routing
 Summary | Full Text:PDF(929.2KB)

A Layout System for Mixed A/D Standard Cell LSI's
Ikuo HARADA Hitoshi KITAZAWA Takao KANEKO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/03/25
Vol. E75-C  No. 3 ; pp. 322-332
Type of Manuscript:  Special Section PAPER (Special Issue on Analog LSI and Related Technology)
Category: 
Keyword: 
analog layoutfloorplanplacementglobal routingchannel routingcrossoverscrosstalk noise
 Summary | Full Text:PDF(993.7KB)