Keyword : gate-level netlist


Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning
Masaru OYA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2308-2319
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware Trojansgate-level netliststeady statesignal transitionlogic test
 Summary | Full Text:PDF(3.4MB)

Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks
Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2320-2326
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware Trojandetectiongate-level netlistmulti-layer neural networksmachine learning
 Summary | Full Text:PDF(324.3KB)

Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest
Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12 ; pp. 2857-2868
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware Trojangate-level netlistTrojan-net featurerandom forestmachine learning
 Summary | Full Text:PDF(1.2MB)

A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features
Kento HASEGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1427-1438
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
hardware Trojangate-level netlistmachine learningsupport vector machine (SVM)neural network (NN)
 Summary | Full Text:PDF(1MB)

Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching
Masaru OYA Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2335-2347
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
hardware Trojansgate-level netlista quantitative criterionpattern matchingdesign phase
 Summary | Full Text:PDF(1.8MB)

A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists
Masaru OYA Youhua SHI Noritaka YAMASHITA Toshihiko OKAMURA Yukiyasu TSUNOO Satoshi GOTO Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2537-2546
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
hardware Trojansgolden-IC freeclassificationidentificationgate-level netlist
 Summary | Full Text:PDF(2.3MB)