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Keyword : gate delay

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Qiang LI Bin LIN Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2011/05/01 Vol. E94-A No. 5 pp. 1201-1209 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: static timing analysis, gate delay, effective capacitance, non-iterative,
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Gate Delay Estimation in STA under Dynamic Power Supply Noise Takaaki OKUMURA Fumihiro MINAMI Kenji SHIMAZAKI Kimihiko KUWADA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/12/01 Vol. E93-A No. 12 pp. 2447-2455 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: power supply noise, gate delay, timing analysis,
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Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model Minglu JIANG Zhangcai HUANG Atsushi KUROKAWA Shuai FANG Yasuaki INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/10/01 Vol. E92-A No. 10 pp. 2531-2539 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Nonlinear Problems Keyword: static timing analysis, gate delay, effective capacitance, Thevenin model,
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A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads Zhangcai HUANG Atsushi KUROKAWA Yasuaki INOUE Junfa MAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/10/01 Vol. E88-A No. 10 pp. 2562-2569 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Keyword: static timing analysis, gate delay, CMOS inverter, effective capacitance, interconnect loads,
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Power Estimation and Reduction of CMOS Circuits Considering Gate Delay Hiroaki UEDA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1999/01/20 Vol. E82-D No. 1 pp. 301-308 Type of Manuscript: PAPER Category: Computer Systems Keyword: CMOS circuit, low power design, gate delay, transition probability, switching activity,
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Analytical Formulas of Output Waveform and Short-Circuit Power Dissipation for Static CMOS Gates Driving a CRC π Load Akio HIRATA Hidetoshi ONODERA Keikichi TAMARU
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/03/20 Vol. E81-A No. 3 pp. 462-469 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems) Category: Keyword: short-circuit power dissipation, short-circuit current, resistive-capacitive load, CRC π load, output waveform, gate delay,
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A CMOS Time-to-Digital Converter LSI with Half-Nanosecond Resolution Using a Ring Gate Delay Line Takamoto WATANABE Yasuaki MAKINO Yoshinori OHTSUKA Shigeyuki AKITA Tadashi HATTORI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1993/12/20 Vol. E76-C No. 12 pp. 1774-1779 Type of Manuscript: Special Section PAPER (Special Issue on ASICs for Automotive Electronics) Category: Keyword: time measurement, gate delay, inverter, phase comparator, A/D converter,
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