IEICE SEARCH SYSTEM

Keyword : functional decomposition

BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades Munehiro MATSUURA Tsutomu SASAO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/12/01 Vol. E90-A No. 12 pp. 2762-2769 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis and Verification Keyword: incompletely specified function, characteristic function, binary decision diagram, functional decomposition, LUT cascade,
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Design Methods of Radix Converters Using Arithmetic Decompositions Yukihiro IGUCHI Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2007/06/01 Vol. E90-D No. 6 pp. 905-914 Type of Manuscript: PAPER Category: Computer Components Keyword: radix converter, LUT cascades, FPGA, functional decomposition,
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A PC-Based Logic Simulator Using a Look-Up Table Cascade Emulator Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2006/12/01 Vol. E89-A No. 12 pp. 3471-3481 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Simulation and Verification Keyword: LUT cascade, bdd_for_cf, functional decomposition,
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A Design Algorithm for Sequential Circuits Using LUT Rings Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3342-3350 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: reconfigurable architecture, LUT cascade, BDD_for_CF, functional decomposition,
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An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs Yusuke MATSUNAGA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-A No. 12 pp. 2715-2724 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: functional decomposition, BDDs, logic synthesis, FPGA,
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A General Framework to Use Various Decomposition Methods for LUT Network Synthesis Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/11/01 Vol. E84-A No. 11 pp. 2915-2922 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: functional decomposition, algebraic decomposition, field programmable gate array (FPGA), look-up table (LUT),
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Functional Decomposition with Application to LUT-Based FPGA Synthesis Jian QIAO Kunihiro ASADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/08/01 Vol. E84-A No. 8 pp. 2004-2013 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, functional decomposition, compatibility class encoding, LUT-based FPGAs,
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An Efficient Method for Finding an Optimal Bi-Decomposition Shigeru YAMASHITA Hiroshi SAWADA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/20 Vol. E81-A No. 12 pp. 2529-2537 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: functional decomposition, bi-decomposition, AND, XOR, look-up table,
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Logic Synthesis for Look-Up Table Based FPGAs Using Functional Decomposition and Boolean Resubstitution Hiroshi SAWADA Takayuki SUYAMA Akira NAGOYA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/10/20 Vol. E80-D No. 10 pp. 1017-1023 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Design Keyword: FPGA, look-up table (LUT), functional decomposition, Boolean resubstitution, support minimization,
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Overlapped Decompositions for Communication Complexity Driven Multilevel Logic Synthesis Kuo-Hua WANG Ting-Ting HWANG Cheng CHEN
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/09/20 Vol. E76-D No. 9 pp. 1075-1084 Type of Manuscript: Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design) Category: Logic Synthesis Keyword: communication complexity, functional decomposition, overlapped decomposition, globals, Decomposition Don't Cares (DDC).,
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