Keyword : flash memory


RRWL: Round Robin-Based Wear Leveling Using Block Erase Table for Flash Memory
Seon Hwan KIM Ju Hee CHOI Jong Wook KWAK 
Publication:   
Publication Date: 2017/05/01
Vol. E100-D  No. 5 ; pp. 1124-1127
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
flash memorywear levelinghidden cold block problembit array tableblock erase table
 Summary | Full Text:PDF(1.9MB)

A Dynamic Switching Flash Translation Layer Based on Page-Level Mapping
Dongchul PARK Biplob DEBNATH David H.C. DU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2016/06/01
Vol. E99-D  No. 6 ; pp. 1502-1511
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
FTLflash translation layerCFTLSSDflash memory
 Summary | Full Text:PDF(1.4MB)

Flash Code Utilizing Binary-Indexed Slice Encoding and Resizable-Clusters
Michael Joseph TAN Yuichi KAJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2360-2367
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
flash codeflash memorybinary-indexedresizable-cluster method
 Summary | Full Text:PDF(783KB)

Bidirectional Limited-Magnitude Error Correction Codes for Flash Memories
Myeongwoon JEON Jungwoo LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7 ; pp. 1602-1608
Type of Manuscript:  PAPER
Category: Coding Theory
Keyword: 
flash memoryerror correction codeslimited magnitude errorsbidirectional errors
 Summary | Full Text:PDF(2MB)

Flash-Aware Page Management Policy of a Navigation-Specialized Mobile DBMS for an Incremental Map Update
KyoungWook MIN JeongDan CHOI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/05/01
Vol. E96-D  No. 5 ; pp. 1211-1214
Type of Manuscript:  LETTER
Category: Data Engineering, Web Information Systems
Keyword: 
mobile DBMSflash memorydatabase page managementmobile navigationnavigation map update
 Summary | Full Text:PDF(1.2MB)

The Expected Write Deficiency of Index-Less Indexed Flash Codes
Yuichi KAJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2130-2138
Type of Manuscript:  Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Coding Theory
Keyword: 
flash codeflash memoryindex-less indexed flash coderandom walk
 Summary | Full Text:PDF(347.5KB)

Comparative Analysis of Bandgap-Engineered Pillar Type Flash Memory with HfO2 and S3N4 as Trapping Layer
Sang-Youl LEE Seung-Dong YANG Jae-Sub OH Ho-Jin YUN Kwang-Seok JEONG Yu-Mi KIM Hi-Deok LEE Ga-Won LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/05/01
Vol. E95-C  No. 5 ; pp. 831-836
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
SOHOShigh-kgate-all-aroundprogram/erase speedflash memory
 Summary | Full Text:PDF(2.2MB)

Enhancing Endurance of Huge-Capacity Flash Storage Systems by Selectively Replacing Data Blocks
Wei-Neng WANG Kai NI Jian-She MA Zong-Chao WANG Yi ZHAO Long-Fa PAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/02/01
Vol. E95-D  No. 2 ; pp. 558-564
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
wear levelingflash memoryselective replacementhuge-capacity storage systems
 Summary | Full Text:PDF(1.2MB)

On Improving the Reliability and Performance of the YAFFS Flash File System
Seungjae BAEK Heekwon PARK Jongmoo CHOI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/12/01
Vol. E94-D  No. 12 ; pp. 2528-2532
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
flash memoryfile systemmount speedperformance evaluationgarbage collection
 Summary | Full Text:PDF(938.6KB)

Adaptive Interference Mitigation for Multilevel Flash Memory Devices
Myeongwoon JEON Kyungchul KIM Sungkyu CHUNG Seungjae CHUNG Beomju SHIN Jungwoo LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11 ; pp. 2453-2457
Type of Manuscript:  LETTER
Category: Analog Signal Processing
Keyword: 
flash memoryinterference cancellationinterference mitigationerror correction
 Summary | Full Text:PDF(410.6KB)

An Empirical Study of FTL Performance in Conjunction with File System Pursuing Data Integrity
In Hwan DOH Myoung Sub SHIM Eunsam KIM Jongmoo CHOI Donghee LEE Sam H. NOH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/08/01
Vol. E93-D  No. 8 ; pp. 2302-2305
Type of Manuscript:  LETTER
Category: Software System
Keyword: 
Flash Translation Layer (FTL)flash memoryfile systemmetadatanon-volatile RAMwrite cache
 Summary | Full Text:PDF(195.5KB)

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices
Seongjae CHO Jung Hoon LEE Yoon KIM Jang-Gn YUN Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5 ; pp. 596-601
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Flash/Advanced Memory
Keyword: 
NANDflash memoryprogram inhibitionself-boostingFinFETdevice simulation
 Summary | Full Text:PDF(1.2MB)

NVFAT: A FAT-Compatible File System with NVRAM Write Cache for Its Metadata
In Hwan DOH Hyo J. LEE Young Je MOON Eunsam KIM Jongmoo CHOI Donghee LEE Sam H. NOH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/05/01
Vol. E93-D  No. 5 ; pp. 1137-1146
Type of Manuscript:  PAPER
Category: Software Systems
Keyword: 
non-volatile RAM (NVRAM)flash memoryfile systemmetadataflash translation layer (FTL)
 Summary | Full Text:PDF(885.3KB)

SONOS-Type Flash Memory with HfO2 Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition
Jae Sub OH Kwang Il CHOI Young Su KIM Min Ho KANG Myeong Ho SONG Sung Kyu LIM Dong Eun YOO Jeong Gyu PARK Hi Deok LEE Ga Won LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/05/01
Vol. E93-C  No. 5 ; pp. 590-595
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: Flash/Advanced Memory
Keyword: 
SONOSSOHOSflash memoryhigh-kHfO2nonvolatile memoryAtomic Layer Deposition
 Summary | Full Text:PDF(1.9MB)

A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
Shinya KAJIYAMA Masamichi FUJITO Hideo KASAI Makoto MIZUNO Takanori YAMAGUCHI Yutaka SHINAGAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/10/01
Vol. E92-C  No. 10 ; pp. 1258-1264
Type of Manuscript:  Special Section PAPER (Special Section on Hardware and Software Technologies on Advanced Microprocessors)
Category: 
Keyword: 
flash memorymicrocontrollerdual-coreshared ROMpipelinesense amplifier
 Summary | Full Text:PDF(1.6MB)

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
Doo-Hyun KIM Il Han PARK Seongjae CHO Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5 ; pp. 659-663
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
SONOSflash memorynitride-based charge trap memoryretentionmulti-bitdouble gate
 Summary | Full Text:PDF(623KB)

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
Yoon KIM Seongjae CHO Gil Sung LEE Il Han PARK Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/05/01
Vol. E92-C  No. 5 ; pp. 653-658
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
NANDflash memorystacked NANDvertical channel
 Summary | Full Text:PDF(717.8KB)

FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs
Hochul LEE Youngchang YOON Ickhyun SONG Hyungcheol SHIN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5 ; pp. 776-779
Type of Manuscript:  Special Section LETTER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
random telegraph signal noiseFN stressflash memoryMOSFET
 Summary | Full Text:PDF(662.3KB)

A Design of Constant-Charge-Injection Programming Scheme for AG-AND Flash Memories Using Array-Level Analytical Model
Shinya KAJIYAMA Ken'ichiro SONODA Kazuo OTSUGA Hideaki KURATA Kiyoshi ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 526-533
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
flash memoryAG-ANDmodelingconstant-charge-injection programminglucky electron model
 Summary | Full Text:PDF(1.1MB)

A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology
Hideaki KURATA Satoshi NODA Yoshitaka SASAGO Kazuo OTSUGA Tsuyoshi ARIGANE Tetsufumi KAWAMURA Takashi KOBAYASHI Hitoshi KUME Kazuki HOMMA Teruhiko ITO Yoshinori SAKAMOTO Masahiro SHIMIZU Yoshinori IKEDA Osamu TSUCHIYA Kazunori FURUSAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/11/01
Vol. E90-C  No. 11 ; pp. 2146-2156
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
flash memorymultilevelinversion-layer-bit-lineAG-AND
 Summary | Full Text:PDF(2.3MB)

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories
Kazuo OTSUGA Hideaki KURATA Satoshi NODA Yoshitaka SASAGO Tsuyoshi ARIGANE Tetsufumi KAWAMURA Takashi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 772-778
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
flash memoryAG-ANDmultilevel technologyconstant-charge-injection programming
 Summary | Full Text:PDF(999.8KB)

A 130-nm CMOS 95-mm2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput
Hideaki KURATA Shunichi SAEKI Takashi KOBAYASHI Yoshitaka SASAGO Tsuyoshi ARIGANE Keiichi YOSHIDA Yoshinori TAKASE Takayuki YOSHITAKE Osamu TSUCHIYA Yoshinori IKEDA Shunichi NARUMI Michitaro KANAMITSU Kazuto IZAWA Kazunori FURUSAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/10/01
Vol. E89-C  No. 10 ; pp. 1469-1479
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
flash memoryAG-ANDmultilevelhigh speed programmingCCIP
 Summary | Full Text:PDF(2.1MB)

Novel Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric Double Gate
Kuk-Hwan KIM Hyunjin LEE Yang-Kyu CHOI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/05/01
Vol. E89-C  No. 5 ; pp. 578-584
Type of Manuscript:  Special Section PAPER (Special Section on Fundamental and Application of Advanced Semiconductor Devices)
Category: Si Devices and Processes
Keyword: 
MONOSSONOSFowler-Nordheim tunnelingflash memoryasymmetric double gatenonvolatile memory
 Summary | Full Text:PDF(984.1KB)

Trends in High-Density Flash Memory Technologies
Takashi KOBAYASHI Hideaki KURATA Katsutaka KIMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/10/01
Vol. E87-C  No. 10 ; pp. 1656-1663
Type of Manuscript:  Special Section PAPER (Special Section on New Era of Nonvolatile Memories)
Category: Flash Memory
Keyword: 
flash memoryhigh densityAG-ANDmultilevelhigh-speed programming
 Summary | Full Text:PDF(1.1MB)

Forward Bias Enhanced Channel Hot Electron Injection for Low-Level Programming Improvement in Multilevel Flash Memory
Caleb Yu-Sheng CHO Ming-Jer CHEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/07/01
Vol. E87-C  No. 7 ; pp. 1204-1207
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
flash memorymultilevelstaircase programming
 Summary | Full Text:PDF(561.3KB)

A Paired MOS Charge Pump for Low Voltage Operation
Jin-Hyeok CHOI Seong-Ik CHO Mu-Hun PARK Young-Hee KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/05/01
Vol. E86-C  No. 5 ; pp. 859-863
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
charge pumpflash memoryhigh-voltage generatorlow-voltage operation
 Summary | Full Text:PDF(483.9KB)

A High-Speed Current-Mode Multilevel Identifying Circuit for Flash Memories
Hongchin LIN Funian LIANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/02/01
Vol. E86-C  No. 2 ; pp. 229-235
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
current-modemultilevel identifying circuitflash memorysense amplifieroffset
 Summary | Full Text:PDF(774.6KB)

An Effective Flash Memory Manager for Reliable Flash Memory Space Management
Han-joon KIM Sang-goo LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/06/01
Vol. E85-D  No. 6 ; pp. 950-964
Type of Manuscript:  PAPER
Category: Databases
Keyword: 
flash memoryloggingcleaning algorithmcycle levelingdata collection
 Summary | Full Text:PDF(1.3MB)

Review of Device Technologies of Flash Memories
Takahiro OHNAKADO Natsuo AJIKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/06/01
Vol. E84-C  No. 6 ; pp. 724-733
Type of Manuscript:  INVITED PAPER (Special Issue on Nonvolatile Memories)
Category: Flash Memories
Keyword: 
flash memorynon-volatile semiconductor memoryfloating gate
 Summary | Full Text:PDF(864.3KB)

Process Synthesis Using TCAD: A Mixed-Signal Case Study
Michael SMAYLING John RODRIGUEZ Alister YOUNG Ichiro FUJII 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 983-991
Type of Manuscript:  INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
process integrationprocess recipescomponentsmixed-signal processflash memoryLDMOSESD circuit
 Summary | Full Text:PDF(559.5KB)

A High Voltage Generator Using Charge Pump Circuit for Low Voltage Flash Memories
Kyeng-Won MIN Shi-Ho KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/05/25
Vol. E82-C  No. 5 ; pp. 781-784
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
high voltage generatorcharge pump circuitflash memory
 Summary | Full Text:PDF(173KB)

New Write/Erase Operation Technology for Flash EEPROM Cells to lmprove the Read Disturb Characteristics
Tetsuo ENDOH Hirohisa IIZUKA Riichirou SHIROTA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/10/25
Vol. E80-C  No. 10 ; pp. 1317-1323
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
flash memoryread disturb characteristicswrite/erase operationstress leakage current
 Summary | Full Text:PDF(585.3KB)

New Reduction Mechanism of the Stress Leakage Current Based on the Deactivation of Step Tunneling Sites for Thin Oxide Films
Tetsuo ENDOH Kazuyosi SHIMIZU Hirohisa IIZUKA Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/10/25
Vol. E80-C  No. 10 ; pp. 1310-1316
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
thin oxide filmsstress leakage currentflash memorystep tonneling
 Summary | Full Text:PDF(499.7KB)

Tunnel Oxynitride Film Formation for Highly Reliable Flash Memory
Tomiyuki ARAKAWA Ryoichi MATSUMOTO Takahisa HAYASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 819-824
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
flash memoryoxynitride tunnel filmendurancedisturbanceretention
 Summary | Full Text:PDF(551.7KB)

A Novel Sensing Scheme with On-Chip Page Copy for Flexible Voltage NAND Flash Memories
Hiroshi NAKAMURA Jun-ichi MIYAMOTO Ken-ichi IMAMIYA Yoshihisa IWATA Yoshihisa SUGIURA Hideko OODAIRA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 836-844
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
flash memorysense amplifierbit-by-bit program verifycapacitive couplingpage copy
 Summary | Full Text:PDF(853.9KB)

2V/120 ns Embedded Flash EEPROM Circuit Technology
Horoshige HIRANO Toshiyuki HONDA Shigeo CHAYA Takahiro FUKUMOTO Tatsumi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 825-831
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Nonvolatile memories
Keyword: 
flash memorylow voltage operationerase algorithmboost circuit
 Summary | Full Text:PDF(535.3KB)

A Novel Threshold Voltage Distribution Measuring Technique for Flash EEPROM Devices
Toshihiko HIMENO Naohiro MATSUKAWA Hiroaki HAZAMA Koji SAKUI Masamitsu OSHIKIRI Kazunori MASUDA Kazushige KANDA Yasuo ITOH Jin-ichi MIYAMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/02/25
Vol. E79-C  No. 2 ; pp. 145-151
Type of Manuscript:  Special Section PAPER (Special Issue on Microelectronic Test Structures)
Category: Device and Circuit Characterization
Keyword: 
flash memoryVth distributionreliabilityNAND flashnonvolatile memory
 Summary | Full Text:PDF(806.8KB)

A 65 ns 3 V-only NAND-Flash Memory with New Verify Scheme and Folded Bit-Line Architecture
Hiromi NOBUKATA Kenichi SATORI Shinji HIRAMATSU Hideki ARAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 818-824
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memoryNANDfolded bit line verify readcharge pump
 Summary | Full Text:PDF(529.3KB)

Programming and Program-Verification Methods for Low-Voltage Flash Memories Using a Sector Programming Scheme
Katsutaka KIMURA Toshihiro TANAKA Masataka KATO Tetsuo ADACHI Keisuke OGURA Hitoshi KUME 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 832-837
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memoryprogrameraseFowler-Nordheim tunnelingsector
 Summary | Full Text:PDF(504.8KB)

Design of a 3.3 V Single Power-Supply 64 Mbit Flash Memory with Dynamic Bit-Line Latch (DBL) Programming Scheme
Hiroshi SUGAWARA Toshio TAKESHIMA Hiroshi TAKADA Yoshiaki S. HISAMUNE Kohji KANAMORI Takeshi OKAZAWA Tatsunori MUROTANI Isao SASAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/07/25
Vol. E78-C  No. 7 ; pp. 825-831
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memory Device, Circuit, Architecture and Application Technologies for Multimedia Age)
Category: 
Keyword: 
flash memory64 Mbitmulti-bit programmingdata registerhierarchical
 Summary | Full Text:PDF(664.9KB)

A High Capacitive Coupling Ratio (HiCR) Cell for Single 3 Volt Power Supply Flash Memories
Kohji KANAMORI Yosiaki S. HISAMUNE Taishi KUBOTA Yoshiyuki SUZUKI Masaru TSUKIJI Eiji HASEGAWA Akihiko ISHITANI Takeshi OKAZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1296-1302
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: Non-volatile Memory
Keyword: 
F-N tunnelingflash memoryoxynitridelow power supply
 Summary | Full Text:PDF(692.8KB)

Improved Array Architectures of DINOR for 0.5 µm 32 M and 64 Mbit Flash Memories
Hiroshi ONODA Yuichi KUNORI Kojiro YUZURIHA Shin-ichi KOBAYASHI Kiyohiko SAKAKIBARA Makoto OHI Atsushi FUKUMOTO Natsuo AJIKA Masahiro HATANAKA Hirokazu MIYOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1279-1286
Type of Manuscript:  Special Section PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: Non-volatile Memory
Keyword: 
Fowler-Nordheim tunnelingvirtual ground arrayflash memoryNORasymmetrical source/drain structure
 Summary | Full Text:PDF(1MB)

Sub-Halfmicron Flash Memory Technologies
Koji SAKUI Fujio MASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/08/25
Vol. E77-C  No. 8 ; pp. 1251-1259
Type of Manuscript:  INVITED PAPER (Special Section on High Speed and High Density Multi Functional LSI Memories)
Category: Non-volatile Memory
Keyword: 
magnetic memorycore memoryEEPROMflash memoryNAND EEPROM
 Summary | Full Text:PDF(705.3KB)

A Symmetrical Side Wall (SSW)-DSA Cell and the Channel Erasing Scheme for a 64 Mbit Flash Memory
Ken-ichi OYAMA Noriaki KODAMA Hiroki SHIRAI Kenji SAITOH Yosiaki S. HISAMUNE Takeshi OKAZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/11/25
Vol. E75-C  No. 11 ; pp. 1358-1363
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: 
Keyword: 
flash memory64 MbitDSA structureerasing schemecharge pumping
 Summary | Full Text:PDF(543.2KB)