Keyword : field-programmable gate array (FPGA)


A Compact Matched Filter Bank for an Optical ZCZ Sequence Set with Zero-Correlation Zone 2z
Yasuaki OHIRA Takahiro MATSUMOTO Hideyuki TORII Yuta IDA Shinya MATSUFUJI 
Publication:   
Publication Date: 2018/01/01
Vol. E101-A  No. 1 ; pp. 195-198
Type of Manuscript:  Special Section LETTER (Special Section on Wideband Systems)
Category: 
Keyword: 
optical communicationoptical M-ary spread spectrum (M-ary/SS) systemoptical zero-correlation zone (ZCZ) sequencematched filter bank (MFB)field-programmable gate array (FPGA)
 Summary | Full Text:PDF(475.9KB)

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme
Daisuke SUZUKI Takahiro HANYU 
Publication:   
Publication Date: 2017/08/01
Vol. E100-D  No. 8 ; pp. 1618-1624
Type of Manuscript:  Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
Category: VLSI Architecture
Keyword: 
field-programmable gate array (FPGA)power gatingmagnetic tunnel junction (MTJ) deviceand low power digital
 Summary | Full Text:PDF(933KB)

A Compact Matched Filter Bank for a Mutually Orthogonal ZCZ Sequence Set Consisting of Ternary Sequence Pairs
Takahiro MATSUMOTO Hideyuki TORII Yuta IDA Shinya MATSUFUJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2595-2600
Type of Manuscript:  Special Section LETTER (Special Section on Signal Design and Its Applications in Communications)
Category: Sequences
Keyword: 
Hadamard sequencezero-correlation zone (ZCZ) sequencemutually orthogonal setmatched filter bankfield-programmable gate array (FPGA)
 Summary | Full Text:PDF(849.4KB)

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption
Yohei HORI Toshihiro KATASHITA Hirofumi SAKANE Kenji TODA Akashi SATOH 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/11/01
Vol. E96-D  No. 11 ; pp. 2333-2343
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
dynamic partial reconfiguration (DPR)field-programmable gate array (FPGA)Advanced Encryption Standard (AES)Galois/Counter Mode (GCM)authenticated encryption
 Summary | Full Text:PDF(1.1MB)

A Secure Content Delivery System Based on a Partially Reconfigurable FPGA
Yohei HORI Hiroyuki YOKOYAMA Hirofumi SAKANE Kenji TODA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/05/01
Vol. E91-D  No. 5 ; pp. 1398-1407
Type of Manuscript:  Special Section PAPER (Special Section on Information and Communication System Security)
Category: Contents Protection
Keyword: 
field-programmable gate array (FPGA)partial run-time reconfiguration (RTR)content protectiondigital rights management (DRM)
 Summary | Full Text:PDF(840.1KB)