IEICE SEARCH SYSTEM

Keyword : fault diagnosis

Accurate Diagnosis in Computer Networks Using Unicast End-to-End Measurements Yan QIAO Xuesong QIU Luoming MENG
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2013/02/01 Vol. E96-B No. 2 pp. 522-532 Type of Manuscript: PAPER Category: Network Keyword: network tomography, fault diagnosis, loss inference,
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Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2012/04/01 Vol. E95-D No. 4 pp. 1093-1100 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, test generation, transition faults, stuck-at ATPG,
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Reducing the Inaccuracy Caused by Inappropriate Time Window in Probabilistic Fault Localization Jianxin LIAO Cheng ZHANG Tonghong LI Xiaomin ZHU
Publication: IEICE TRANSACTIONS on Communications Publication Date: 2011/01/01 Vol. E94-B No. 1 pp. 128-138 Type of Manuscript: PAPER Category: Network Management/Operation Keyword: fault diagnosis, fault localization, fault propagation model, time window, event-driven,
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Application of Similarity in Fault Diagnosis of Power Electronics Circuits Wang RONGJIE Zhan YIJU Chen MEIQIAN Zhou HAIFENG Guo KEWEI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/06/01 Vol. E93-A No. 6 pp. 1190-1195 Type of Manuscript: PAPER Category: Circuit Theory Keyword: S transforms, similarity, fault diagnosis, power electronics circuit,
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A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information Koji YAMAZAKI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 661-666 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, open fault, BIST, pass/fail information,
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A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits Yuta YAMATO Yusuke NAKAMURA Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 667-674 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: Fault Diagnosis Keyword: fault diagnosis, X-fault model, per-test, via,
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Fault Detection and Diagnosis of Manipulator Based on Probabilistic Production Rule Shinkichi INAGAKI Koudai HAYASHI Tatsuya SUZUKI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2007/11/01 Vol. E90-A No. 11 pp. 2488-2495 Type of Manuscript: Special Section PAPER (Special Section on Concurrent/Hybrid Systems: Theory and Applications) Category: Keyword: probabilistic production rule, fault detection, fault diagnosis, manipulator,
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A Per-Test Fault Diagnosis Method Based on the X-Fault Model Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/11/01 Vol. E89-D No. 11 pp. 2756-2765 Type of Manuscript: PAPER Category: Dependable Computing Keyword: fault diagnosis, per-test, X-fault model,
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Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2006/03/01 Vol. E89-D No. 3 pp. 1165-1172 Type of Manuscript: PAPER Category: Dependable Computing Keyword: BIST, fault diagnosis, error identification, at-speed test, low speed tester,
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On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2005/04/01 Vol. E88-D No. 4 pp. 703-710 Type of Manuscript: PAPER Category: Computer Components Keyword: fault diagnosis, I_DDQ, transistor leakage fault model, multiple power supply, circuit partitioning,
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Layout-Based Detection Technique of Line Pairs with Bridging Fault Using I_DDQ Masaru SANADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 557-563 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Fault Detection Keyword: I_DDQ, bridging fault, logic, layout structure, fault diagnosis,
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Diagnosability of Butterfly Networks under the Comparison Approach Toru ARAKI Yukio SHIBATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/05/01 Vol. E85-A No. 5 pp. 1152-1160 Type of Manuscript: PAPER Category: Graphs and Networks Keyword: fault diagnosis, comparison approach, diagnosability, butterfly network,
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Optimal Diagnosable Systems on Cayley Graphs Toru ARAKI Yukio SHIBATA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/02/01 Vol. E85-A No. 2 pp. 455-462 Type of Manuscript: PAPER Category: Graphs and Networks Keyword: fault diagnosis, PMC models, highly structured systems, Cayley graphs, multiprocessor systems,
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Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using I_DDQ Masaru SANADA Hiromu FUJIOKA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/05/20 Vol. E83-A No. 5 pp. 842-850 Type of Manuscript: Special Section PAPER (Special Section on Reliability Theory and Its Applications) Category: Keyword: I_DDQ, visual abnormalities, logic LSI, fault diagnosis, physical damages,
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OTA-C Based BIST Structure for Analog Circuits Cheng-Chung HSU Wu-Shiung FENG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2000/04/20 Vol. E83-A No. 4 pp. 771-773 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: built-in self-test (BIST), operational transconductance amplifier (OTA), analog circuit, fault diagnosis, testing,
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Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 706-715 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: combinational circuit, fault diagnosis, multiple delay fault, diagnostic rules, path-tracing method, test-pairs for marginal delays,
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Transistor Leakage Fault Diagnosis for CMOS Circuits Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 697-705 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: Fault Diagnosis Keyword: fault diagnosis, transistor leakage fault, I_DDQ, primary output, fault simulation, diagnostic test generation,
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Complete Diagnosis Patterns for Wiring Interconnects Sungju PARK Gueesang LEE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/04/20 Vol. E81-A No. 4 pp. 672-676 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: boundary scan, shorted nets fault, stuck-at fault, fault detection, fault diagnosis, interconnect test,
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Transistor Leakage Fault Diagnosis with I_DDQ and Logic Information Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/04/20 Vol. E81-D No. 4 pp. 372-381 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: fault diagnosis, transistor leakage fault, I_DDQ testing, fault simulation, diagnostic vector generation,
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A CAD-Based Approach to Fault Diagnosis of CMOS LSI with Single Fault Using Abnormal Iddq Masaru SANADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/10/20 Vol. E80-A No. 10 pp. 1945-1954 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: CMOSLSI, Iddq, single faulty mode, fault diagnosis, logic simulation,
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On the Multiple Bridge Fault Diagnosis of Baseline Multistage Interconnection Networks^* Fabrizio LOMBARDI Nohpill PARK Susumu HORIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/08/20 Vol. E79-D No. 8 pp. 1168-1179 Type of Manuscript: Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing) Category: Fault Diagnosis/Tolerance Keyword: multistage interconnection network, fault diagnosis, fault tolerance, bridge fault, multiple faults,
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On-Line Fault Diagnosis by Using Fuzzy Cognitive Map Keesang LEE Sungho KIM Masatoshi SAKAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/06/20 Vol. E79-A No. 6 pp. 921-927 Type of Manuscript: PAPER Category: Reliability and Fault Analysis Keyword: fuzzy cognitive map, temporal associative memory, fault diagnosis, incipient fault diagnosis,
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A Single Bridging Fault Location Technique for CMOS Combinational Circuits Koji YAMAZAKI Teruhiko YAMADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 817-821 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: fault diagnosis, bridging fault, CMOS, combinational circuit,
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Design of Repairable Cellular Arrays on Multiple-Valued Logic Naotake KAMIURA Yutaka HATA Kazuharu YAMATO
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1994/08/20 Vol. E77-D No. 8 pp. 877-884 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: multiple-valued logic, ecllular array, fault diagnosis, repair, design for testability,
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E-Beam Static Fault Imaging with a CAD Interface and Its Application to Marginal Fault Diagnosis Norio KUJI Kiyoshi MATSUMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1994/04/20 Vol. E77-C No. 4 pp. 552-559 Type of Manuscript: Special Section PAPER (Special Issue on LSI Failure Analysis) Category: Keyword: E-beam testing, fault diagnosis, marginal fault, fault image, fault tracing,
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SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits Koji YAMAZAKI Teruhiko YAMADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1993/07/20 Vol. E76-D No. 7 pp. 826-831 Type of Manuscript: Special Section PAPER (Special Issue on VLSI Testing and Testable Design) Category: Keyword: fault diagnosis, gate-level fault, combinational circuit, probing,
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A Testable Design of Sequential Circuits under Highly Observable Condition WEN Xiaoqing Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1992/05/20 Vol. E75-D No. 3 pp. 334-341 Type of Manuscript: PAPER Category: Fault Tolerant Computing Keyword: design for testability, highly observable testing, fault diagnosis, sequential circuit, circuit modification,
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