Keyword : fault diagnosis


Fault Analysis and Diagnosis of Coaxial Connectors in RF Circuits
Rui JI Jinchun GAO Gang XIE Qiuyan JIN 
Publication:   
Publication Date: 2017/11/01
Vol. E100-C  No. 11 ; pp. 1052-1060
Type of Manuscript:  PAPER
Category: Electromechanical Devices and Components
Keyword: 
coaxial connectorfailure featurehigh frequencyfault diagnosisneural network
 Summary | Full Text:PDF(909.3KB)

A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line
Yoshinobu HIGAMI Senling WANG Hiroshi TAKAHASHI Shin-ya KOBAYASHI Kewal K. SALUJA 
Publication:   
Publication Date: 2017/09/01
Vol. E100-D  No. 9 ; pp. 2224-2227
Type of Manuscript:  LETTER
Category: Dependable Computing
Keyword: 
fault diagnosisbridging faultsclock lines
 Summary | Full Text:PDF(554.2KB)

Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories
Masashi IMAI Tomohiro YONEDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/09/01
Vol. E96-D  No. 9 ; pp. 1914-1925
Type of Manuscript:  Special Section PAPER (Special Section on Dependable Computing)
Category: 
Keyword: 
mean time to failurenetwork-on-chipmultiple processor systemfault diagnosispair and swap
 Summary | Full Text:PDF(1.5MB)

Accurate Diagnosis in Computer Networks Using Unicast End-to-End Measurements
Yan QIAO Xuesong QIU Luoming MENG 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/02/01
Vol. E96-B  No. 2 ; pp. 522-532
Type of Manuscript:  PAPER
Category: Network
Keyword: 
network tomographyfault diagnosisloss inference
 Summary | Full Text:PDF(1.6MB)

Generation of Diagnostic Tests for Transition Faults Using a Stuck-At ATPG Tool
Yoshinobu HIGAMI Satoshi OHNO Hironori YAMAOKA Hiroshi TAKAHASHI Yoshihiro SHIMIZU Takashi AIKYO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/04/01
Vol. E95-D  No. 4 ; pp. 1093-1100
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosistest generationtransition faultsstuck-at ATPG
 Summary | Full Text:PDF(502.5KB)

Reducing the Inaccuracy Caused by Inappropriate Time Window in Probabilistic Fault Localization
Jianxin LIAO Cheng ZHANG Tonghong LI Xiaomin ZHU 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/01/01
Vol. E94-B  No. 1 ; pp. 128-138
Type of Manuscript:  PAPER
Category: Network Management/Operation
Keyword: 
fault diagnosisfault localizationfault propagation modeltime windowevent-driven
 Summary | Full Text:PDF(1.4MB)

Application of Similarity in Fault Diagnosis of Power Electronics Circuits
Wang RONGJIE Zhan YIJU Chen MEIQIAN Zhou HAIFENG Guo KEWEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/06/01
Vol. E93-A  No. 6 ; pp. 1190-1195
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
S transformssimilarityfault diagnosispower electronics circuit
 Summary | Full Text:PDF(4.7MB)

A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information
Koji YAMAZAKI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 661-666
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
fault diagnosisopen faultBISTpass/fail information
 Summary | Full Text:PDF(570.7KB)

A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits
Yuta YAMATO Yusuke NAKAMURA Kohei MIYASE Xiaoqing WEN Seiji KAJIHARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/03/01
Vol. E91-D  No. 3 ; pp. 667-674
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSIs)
Category: Fault Diagnosis
Keyword: 
fault diagnosisX-fault modelper-testvia
 Summary | Full Text:PDF(1.4MB)

Fault Detection and Diagnosis of Manipulator Based on Probabilistic Production Rule
Shinkichi INAGAKI Koudai HAYASHI Tatsuya SUZUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/11/01
Vol. E90-A  No. 11 ; pp. 2488-2495
Type of Manuscript:  Special Section PAPER (Special Section on Concurrent/Hybrid Systems: Theory and Applications)
Category: 
Keyword: 
probabilistic production rulefault detectionfault diagnosismanipulator
 Summary | Full Text:PDF(936.3KB)

A Per-Test Fault Diagnosis Method Based on the X-Fault Model
Xiaoqing WEN Seiji KAJIHARA Kohei MIYASE Yuta YAMATO Kewal K. SALUJA Laung-Terng WANG Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/11/01
Vol. E89-D  No. 11 ; pp. 2756-2765
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
fault diagnosisper-testX-fault model
 Summary | Full Text:PDF(829.4KB)

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch
Yoshiyuki NAKAMURA Thomas CLOUQUEUR Kewal K. SALUJA Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/03/01
Vol. E89-D  No. 3 ; pp. 1165-1172
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
BISTfault diagnosiserror identificationat-speed testlow speed tester
 Summary | Full Text:PDF(462.4KB)

On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies
Xiaoqing WEN Seiji KAJIHARA Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/04/01
Vol. E88-D  No. 4 ; pp. 703-710
Type of Manuscript:  PAPER
Category: Computer Components
Keyword: 
fault diagnosisIDDQtransistor leakage fault modelmultiple power supplycircuit partitioning
 Summary | Full Text:PDF(487.3KB)

Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ
Masaru SANADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 557-563
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Fault Detection
Keyword: 
IDDQbridging faultlogiclayout structurefault diagnosis
 Summary | Full Text:PDF(3MB)

Diagnosability of Butterfly Networks under the Comparison Approach
Toru ARAKI Yukio SHIBATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/05/01
Vol. E85-A  No. 5 ; pp. 1152-1160
Type of Manuscript:  PAPER
Category: Graphs and Networks
Keyword: 
fault diagnosiscomparison approachdiagnosabilitybutterfly network
 Summary | Full Text:PDF(511.1KB)

Optimal Diagnosable Systems on Cayley Graphs
Toru ARAKI Yukio SHIBATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/02/01
Vol. E85-A  No. 2 ; pp. 455-462
Type of Manuscript:  PAPER
Category: Graphs and Networks
Keyword: 
fault diagnosisPMC modelshighly structured systemsCayley graphsmultiprocessor systems
 Summary | Full Text:PDF(355.5KB)

Fault Diagnosis Technique for Yield Enhancement of Logic LSI Using IDDQ
Masaru SANADA Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/05/25
Vol. E83-A  No. 5 ; pp. 842-850
Type of Manuscript:  Special Section PAPER (Special Section on Reliability Theory and Its Applications)
Category: 
Keyword: 
IDDQvisual abnormalitieslogic LSIfault diagnosisphysical damages
 Summary | Full Text:PDF(2.7MB)

OTA-C Based BIST Structure for Analog Circuits
Cheng-Chung HSU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/04/25
Vol. E83-A  No. 4 ; pp. 771-773
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
built-in self-test (BIST)operational transconductance amplifier (OTA)analog circuitfault diagnosistesting
 Summary | Full Text:PDF(642.8KB)

Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 706-715
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
combinational circuitfault diagnosismultiple delay faultdiagnostic rulespath-tracing methodtest-pairs for marginal delays
 Summary | Full Text:PDF(814.1KB)

Transistor Leakage Fault Diagnosis for CMOS Circuits
Xiaoqing WEN Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 697-705
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
fault diagnosistransistor leakage faultIDDQprimary outputfault simulationdiagnostic test generation
 Summary | Full Text:PDF(868.3KB)

Complete Diagnosis Patterns for Wiring Interconnects
Sungju PARK Gueesang LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 672-676
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
boundary scanshorted nets faultstuck-at faultfault detectionfault diagnosisinterconnect test
 Summary | Full Text:PDF(427.9KB)

Transistor Leakage Fault Diagnosis with IDDQ and Logic Information
Wen XIAOQING Hideo TAMAMOTO Kewal K. SALUJA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/04/25
Vol. E81-D  No. 4 ; pp. 372-381
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
fault diagnosistransistor leakage faultIDDQ testingfault simulationdiagnostic vector generation
 Summary | Full Text:PDF(985.7KB)

A CAD-Based Approach to Fault Diagnosis of CMOS LSI with Single Fault Using Abnormal Iddq
Masaru SANADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1945-1954
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
CMOSLSIIddqsingle faulty modefault diagnosislogic simulation
 Summary | Full Text:PDF(873.6KB)

On the Multiple Bridge Fault Diagnosis of Baseline Multistage Interconnection Networks*
Fabrizio LOMBARDI Nohpill PARK Susumu HORIGUCHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/08/25
Vol. E79-D  No. 8 ; pp. 1168-1179
Type of Manuscript:  Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
Category: Fault Diagnosis/Tolerance
Keyword: 
multistage interconnection networkfault diagnosisfault tolerancebridge faultmultiple faults
 Summary | Full Text:PDF(1.1MB)

On-Line Fault Diagnosis by Using Fuzzy Cognitive Map
Keesang LEE Sungho KIM Masatoshi SAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/06/25
Vol. E79-A  No. 6 ; pp. 921-927
Type of Manuscript:  PAPER
Category: Reliability and Fault Analysis
Keyword: 
fuzzy cognitive maptemporal associative memoryfault diagnosisincipient fault diagnosis
 Summary | Full Text:PDF(626.4KB)

A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 817-821
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
fault diagnosisbridging faultCMOScombinational circuit
 Summary | Full Text:PDF(398KB)

Design of Repairable Cellular Arrays on Multiple-Valued Logic
Naotake KAMIURA Yutaka HATA Kazuharu YAMATO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1994/08/25
Vol. E77-D  No. 8 ; pp. 877-884
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
multiple-valued logicecllular arrayfault diagnosisrepairdesign for testability
 Summary | Full Text:PDF(672.9KB)

E-Beam Static Fault Imaging with a CAD Interface and Its Application to Marginal Fault Diagnosis
Norio KUJI Kiyoshi MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/04/25
Vol. E77-C  No. 4 ; pp. 552-559
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Failure Analysis)
Category: 
Keyword: 
E-beam testingfault diagnosismarginal faultfault imagefault tracing
 Summary | Full Text:PDF(733.6KB)

SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 826-831
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault diagnosisgate-level faultcombinational circuitprobing
 Summary | Full Text:PDF(455.2KB)

A Testable Design of Sequential Circuits under Highly Observable Condition
WEN Xiaoqing Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3 ; pp. 334-341
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
design for testabilityhighly observable testingfault diagnosissequential circuitcircuit modification
 Summary | Full Text:PDF(660.1KB)