Keyword : false path


A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification
Hiroshi IWATA Satoshi OHTAKE Hideo FUJIWARA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/07/01
Vol. E93-D  No. 7 ; pp. 1857-1865
Type of Manuscript:  PAPER
Category: Information Network
Keyword: 
false pathhigh level testingpath mappingfunctional equivalence
 Summary | Full Text:PDF(348.9KB)

Multi-Cycle Path Detection for Sequential Circuits and Its Application to Real Designs
Hiroyuki HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3176-3183
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
multi-cycle pathfalse pathsequential circuitimplicationATPGmultiple clock
 Summary | Full Text:PDF(414.4KB)

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2515-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
timing verificationmaximum delay analysismultiple clock operationfalse path
 Summary | Full Text:PDF(546.5KB)