Keyword : embedded processor


HOG-Based Object Detection Processor Design Using ASIP Methodology
Shanlin XIAO Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12 ; pp. 2972-2984
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
ASIPhistogram of oriented gradients (HOG)embedded processorcomputer visionobject detection
 Summary | Full Text:PDF(2MB)

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm
Shanlin XIAO Tsuyoshi ISSHIKI Dongju LI Hiroaki KUNIEDA 
Publication:   
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1384-1395
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
ASIPembedded processorcomputer visionobject detectionAdaBoost
 Summary | Full Text:PDF(1.3MB)

A Leakage Efficient Instruction TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/08/01
Vol. E94-D  No. 8 ; pp. 1565-1574
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage powerTLBembedded processor
 Summary | Full Text:PDF(1.3MB)

Core Working Set Based Scratchpad Memory Management
Ning DENG Weixing JI Jiaxin LI Qi ZUO Feng SHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/02/01
Vol. E94-D  No. 2 ; pp. 274-285
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
embedded processorscratchpad memory managementcore working set
 Summary | Full Text:PDF(1.4MB)

A Leakage Efficient Data TLB Design for Embedded Processors
Zhao LEI Hui XU Daisuke IKEBUCHI Tetsuya SUNATA Mitaro NAMIKI Hideharu AMANO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/01/01
Vol. E94-D  No. 1 ; pp. 51-59
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
leakage powerTLBembedded processor
 Summary | Full Text:PDF(921.7KB)

A Partial Access Mechanism on a Register for Low-Cost Embedded Multimedia ASIP
Ha-young JEONG Min-young CHO Won HUR Yong-surk LEE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/07/01
Vol. E91-C  No. 7 ; pp. 1171-1174
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
embedded processorASIPSIMDpartial access
 Summary | Full Text:PDF(270.6KB)

Cooperative Cache System: A Low Power Cache System for Embedded Processors
Gi-Ho PARK Kil-Whan LEE Tack-Don HAN Shin-Dug KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 708-717
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
low power cachecooperative cacheblock sizeassociativityembedded processor
 Summary | Full Text:PDF(1.2MB)

Dynamic Reconfiguration of Cache Indexing in Embedded Processors
Junhee KIM Sung-Soo LIM Jihong KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/03/01
Vol. E90-D  No. 3 ; pp. 637-647
Type of Manuscript:  PAPER
Category: VLSI Systems
Keyword: 
cache indexingcache organizationdynamic reconfigurationembedded processormicroprocessor architecture
 Summary | Full Text:PDF(2MB)

A Hardware Accelerator for JavaTM Platforms on a 130-nm Embedded Processor Core
Tetsuya YAMADA Naohiko IRIE Takanobu TSUNODA Takahiro IRITA Kenji KITAGAWA Ryohei YOSHIDA Keisuke TOYAMA Motoaki SATOYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/02/01
Vol. E90-C  No. 2 ; pp. 523-530
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
embedded processorJavaacceleratorbytecode
 Summary | Full Text:PDF(1.8MB)

An Energy-Efficient Partitioned Instruction Cache Architecture for Embedded Processors
CheolHong KIM SungWoo CHUNG ChuShik JHON 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/04/01
Vol. E89-D  No. 4 ; pp. 1450-1458
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
instruction cachepartitioned cachelow power designdynamic energyembedded processor
 Summary | Full Text:PDF(2.9MB)

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core
Tetsuya YAMADA Masahide ABE Yusuke NITTA Kenji OGURA Manabu KUSAOKE Makoto ISHIKAWA Motokazu OZAWA Kiwamu TAKADA Fumio ARAKAWA Osamu NISHII Toshihiro HATTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 287-294
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Low Power Techniques
Keyword: 
embedded processorclockgated clockflip-flop
 Summary | Full Text:PDF(1.4MB)

Speculative Branch Folding for Pipelined Processors
Sang-Hyun PARK Sungwook YU Jung-Wan CHO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/05/01
Vol. E88-D  No. 5 ; pp. 1064-1066
Type of Manuscript:  LETTER
Category: Computer Systems
Keyword: 
branch foldingspeculativeembedded processorpipeline
 Summary | Full Text:PDF(409.4KB)

An Exact Leading Non-Zero Detector for a Floating-Point Unit
Fumio ARAKAWA Tomoichi HAYASHI Masakazu NISHIBORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 570-575
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP)
Category: Digital
Keyword: 
floating-pointleading non-zeronormalizeembedded processor
 Summary | Full Text:PDF(1011.6KB)

An Embedded Processor Core for Consumer Appliances with 2.8GFLOPS and 36 M Polygons/s FPU
Fumio ARAKAWA Motokazu OZAWA Osamu NISHII Toshihiro HATTORI Takeshi YOSHINAGA Tomoichi HAYASHI Yoshikazu KIYOSHIGE Takashi OKADA Masakazu NISHIBORI Tomoyuki KODAMA Tatsuya KAMEI Makoto ISHIKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3068-3074
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
embedded processorarchitectureFPUpipeline
 Summary | Full Text:PDF(2MB)

Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers
Akihiko HIGUCHI Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/04/01
Vol. E87-A  No. 4 ; pp. 823-829
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
embedded processorpower estimationinstruction-level
 Summary | Full Text:PDF(1.3MB)

A 500-MHz Embedded Out-of-Order Superscalar Microprocessor
Masayuki DAITO Kazumasa SUZUKI Ken-ichi UEHIGASHI Hiroshi MORITA Hitoshi SONODA Nobuhito MORIKAWA Masatoshi MORIYAMA Shoichiro SATO Terumi FUKUDA Saori NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 243-252
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processorRISCout-of-ordersuperpipeline
 Summary | Full Text:PDF(2.2MB)

Branch Micro-Architecture of an Embedded Processor with Split Branch Architecture for Digital Consumer Products
Naohiko IRIE Fumio ARAKAWA Kunio UCHIYAMA Shinichi YOSHIOKA Atsushi HASEGAWA Kevin IADONATE Mark DEBBAGE David SHEPHERD Margaret GEARTY 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 315-322
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
embedded processorSIMDpreloadbranch prediction
 Summary | Full Text:PDF(1.3MB)

A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
Tetsuya YAMADA Makoto ISHIKAWA Yuji OGATA Takanobu TSUNODA Takahiro IRITA Saneaki TAMAKI Kunihiko NISHIYAMA Tatsuya KAMEI Ken TATEZAWA Fumio ARAKAWA Takuichiro NAKAZAWA Toshihiro HATTORI Kunio UCHIYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 253-262
Type of Manuscript:  INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: 
Keyword: 
embedded processorlow powerRISCDSPMAC
 Summary | Full Text:PDF(1.8MB)

Embedded Processor Core with 64-Bit Architecture and Its System-On-Chip Integration for Digital Consumer Products
Kunio UCHIYAMA Fumio ARAKAWA Yasuhiko SAITO Koki NOGUCHI Atsushi HASEGAWA Shinichi YOSHIOKA Naohiko IRIE Takeshi KITAHARA Mark DEBBAGE Andy STURGES 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 139-149
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
embedded processorRISCSIMDsystem-on-chipmultimedia
 Summary | Full Text:PDF(1.6MB)