IEICE SEARCH SYSTEM

Keyword : embedded DRAM

Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor Takahiro SEKI Satoshi AKUI Katsunori SENO Masakatsu NAKAI Tetsumasa MEGURO Tetsuo KONDO Akihiko HASHIGUCHI Hirokazu KAWAHARA Kazuo KUMANO Masayuki SHIMURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2005/04/01 Vol. E88-C No. 4 pp. 520-527 Type of Manuscript: Special Section PAPER (Special Section on Low-Power LSI and Low-Power IP) Category: Digital Keyword: adaptive supply voltage control, autonomous clock frequency control, leakage power compensation, embedded DRAM, wideband bus architecture,
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A 90 mW MPEG-4 Video Codec LSI with the Capability for Core Profile Takashi HASHIMOTO Shunichi KUROMARU Masayoshi TOUJIMA Yasuo KOHASHI Masatoshi MATSUO Toshihiro MORIIWA Masahiro OHASHI Tsuyoshi NAKAMURA Mana HAMADA Yuji SUGISAWA Miki KUROMARU Tomonori YONEZAWA Satoshi KAJITA Takahiro KONDO Hiroki OTSUKI Kohkichi HASHIMOTO Hiromasa NAKAJIMA Taro FUKUNAGA Hiroaki TOIDA Yasuo IIZUKA Hitoshi FUJIMOTO Junji MICHIYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/07/01 Vol. E86-C No. 7 pp. 1374-1384 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: MPEG-4 visual, core profile, hybrid architecture, clock gating, embedded DRAM, low power,
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An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced-on-Chip Tester Naoya WATANABE Fukashi MORISHITA Yasuhiko TAITO Akira YAMAZAKI Tetsushi TANIZAKI Katsumi DOSAKA Yoshikazu MOROOKA Futoshi IGAUE Katsuya FURUE Yoshihiro NAGURA Tatsunori KOMOIKE Toshinori MORIHARA Atsushi HACHISUKA Kazutami ARIMOTO Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-C No. 4 pp. 624-634 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: embedded DRAM, various DRAM macros, low voltage operation, short TAT, BIST,
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Accomplishment of At-Speed BISR for Embedded DRAMs Yoshihiro NAGURA Yoshinori FUJIWARA Katsuya FURUE Ryuji OHMURA Tatsunori KOMOIKE Takenori OKITAKA Tetsushi TANIZAKI Katsumi DOSAKA Kazutami ARIMOTO Yukiyoshi KODA Tetsuo TADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1498-1505 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: at-speed test, BISR, embedded DRAM, test cost reduction,
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A 0.18 µm 32 Mb Embedded DRAM Macro for 3-D Graphics Controller Akira YAMAZAKI Takeshi FUJINO Kazunari INOUE Isamu HAYASHI Hideyuki NODA Naoya WATANABE Fukashi MORISHITA Katsumi DOSAKA Yoshikazu MOROOKA Shinya SOEDA Kazutami ARIMOTO Setsuo WAKE Kazuyasu FUJISHIMA Hideyuki OZAKI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/09/01 Vol. E85-C No. 9 pp. 1697-1708 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: embedded DRAM, system on chip, 3-D graphics concurrent operation,
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A Single Chip Multiprocessor Integrated with High Density DRAM Tadaaki YAMAUCHI Lance HAMMOND Oyekunle A. OLUKOTUN Kazutami ARIMOTO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/08/20 Vol. E82-C No. 8 pp. 1567-1577 Type of Manuscript: PAPER Category: Electronic Circuits Keyword: DRAM, oh-chip DRAM, embedded DRAM, on-chip L2 caches, SRAM caches, multiprocessor, multiprocessor-on-a-chip,
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Large Scale Embedded DRAM Technology Akira YAMAZAKI Tadato YAMAGATA Yutaka ARITA Makoto TANIGUCHI Michihiro YAMADA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/20 Vol. E81-C No. 5 pp. 750-758 Type of Manuscript: INVITED PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: DRAM Keyword: embedded DRAM, system on chip, system LSI,
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Design of 1024-I/Os 3. 84 GB/s High Bandwidth 600 mW Low Power 16 Mb DRAM Macros for Parallel Image Processing RAM Yoshiharu AIMOTO Tohru KIMURA Yoshikazu YABE Hideki HEIUCHI Youetsu NAKAZAWA Masato MOTOMURA Takuya KOGA Yoshihiro FUJITA Masayuki HAMADA Takaho TANIGAWA Hajime NOBUSAWA Kuniaki KOYAMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/05/20 Vol. E81-C No. 5 pp. 759-767 Type of Manuscript: Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs) Category: Keyword: integration of DRAM and logic, embedded DRAM, low power, high memory bandwidth,
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Low-Power and High-Speed Advantages of DRAM-Logic Integration for Multimedia Systems Takao WATANABE Ryo FUJITA Kazumasa YANAGISAWA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1997/12/20 Vol. E80-C No. 12 pp. 1523-1531 Type of Manuscript: INVITED PAPER (Special Issue on Low-Power and High-Speed LSI Technologies) Category: Keyword: DRAM-integrated chip, embedded DRAM, computer graphics, main memory,
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