Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/03/20 Vol. E80-ANo. 3pp. 487-493 Type of Manuscript: Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems) Category: Keyword: super fine-grain parallel processing,
FPGA,
high level synthesize PARTHENON,
inverter reduction,
dynamical system,