Keyword : distributed-register architecture


A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures
Kotaro TERADA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   
Publication Date: 2017/12/01
Vol. E100-A  No. 12 ; pp. 2911-2924
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesismultiple-bitwidthdistributed-register architectureoperation chaininginterconnection delayfloorplan
 Summary | Full Text:PDF(2.3MB)

A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design
Koki IGAWA Masao YANAGISAWA Nozomu TOGAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/07/01
Vol. E99-A  No. 7 ; pp. 1278-1293
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
high-level synthesisprocess variationinterconnection delaydistributed-register architecturescenario
 Summary | Full Text:PDF(2.4MB)

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures
Akira OHCHI Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3169-3179
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisfloorplandistributed-register architecturegeneralized distributed-register architecturelocal registerlocal controller
 Summary | Full Text:PDF(825.7KB)