Keyword : distributed arithmetic


The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning
Hun-Chen CHEN Tian-Sheuan CHANG Jiun-In GUO Chein-Wei JEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/05/01
Vol. E88-C  No. 5 ; pp. 1061-1069
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
discrete Hartley transformdistributed arithmeticcyclic preserving partitioningcomputation sharing
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FPGA Implementation of FIR Filter Using 2-Bit Parallel Distributed Arithmetic
Shiann-Shiun JENG Shu-Ming CHANG Bor-Shuh LAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/05/01
Vol. E87-A  No. 5 ; pp. 1280-1282
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
distributed arithmeticfinite impulse response (FIR) filter
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A Low-Power Implementation Scheme of Interpolation FIR Filters Using Distributed Arithmetic
Sangyun HWANG Gunhee HAN Sungho KANG Jaeseok KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/11/01
Vol. E86-C  No. 11 ; pp. 2346-2350
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
low-power interpolation FIR filterdistributed arithmeticlook-up tabledynamic power consumption
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Analysis of the Convergence Condition of LMS Adaptive Digital Filter Using Distributed Arithmetic
Kyo TAKAHASHI Yoshitaka TSUNEKAWA Norio TAYAMA Kyoushirou SEKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6 ; pp. 1249-1256
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2001 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2001))
Category: 
Keyword: 
distributed arithmeticLMS algorithmadaptive function spaceconvergence conditionoffset bias
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A High-Speed Multiplier-Free Realization of IIR Filter Using ROM's and Elevated Signal Rate
Thanyapat SAKUNKONCHAK Sawasd TANTARATANA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/06/01
Vol. E84-A  No. 6 ; pp. 1479-1487
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000))
Category: 
Keyword: 
multiplier-free realizationdistributed arithmeticpowers-of-two coefficientsROM'scarry-lookahead adders
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High-Performance Multiprocessor Implementation for Block-State Realization of State-Space Digital Filters
Yoshitaka TSUNEKAWA Kyousiro SEKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/06/25
Vol. E77-A  No. 6 ; pp. 944-949
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1993 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC'93))
Category: Digital Signal Processing
Keyword: 
state-space digital filtermultiprocessor implementationblock-state realizationdistributed arithmetic
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A Method for Estimating the Mean-Squared Error of Distributed Arithmetic
Jun TAKEDA Shin-ichi URAMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/01/25
Vol. E77-A  No. 1 ; pp. 272-280
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
error analysismean-squared errordistributed arithmeticDCT/IDCT
 Summary | Full Text:PDF(660.5KB)

Design and Evaluation of Highly Prallel VLSI Processors for 2-D State-Space Digital Filters Using Hierarchical Behavioral Description Language and Synthesizer
Masayuki KAWAMATA Yasushi IWATA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7 ; pp. 837-845
Type of Manuscript:  Special Section PAPER (Special Section on Multidimensional Signal Processing)
Category: Design and Implementation of Multidimensional Digital Filters
Keyword: 
two dimensional state-space digital filtersVLSI processorsdistributed arithmeticbehavioral description languagelogic synthesizer
 Summary | Full Text:PDF(685.8KB)