Keyword : digital arithmetic

Fixed-Width Group CSD Multiplier Design
Yong-Eun KIM  Kyung-Ju CHO  Jin-Gyun CHUNG  Xinming HUANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/06/01
Vol. E93-D  No. 6  pp. 1497-1503
Type of Manuscript: PAPER
Category: Fundamentals of Information Systems
Keyword: 
fixed-width,  GCSD multiplier,  quantization error,  digital arithmetic, 
  Summary |  Full Text:PDF (578.4KB)
Low Power MAC Design with Variable Precision Support
Young-Geun LEE  Han-Sam JUNG  Ki-Seok CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/07/01
Vol. E92-A  No. 7  pp. 1623-1632
Type of Manuscript: PAPER
Category: Digital Signal Processing
Keyword: 
digital arithmetic,  digital signal processors,  constant multiplication,  power consumption, 
  Summary |  Full Text:PDF (1.6MB)
Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients
Yong-Eun KIM  Kyung-Ju CHO  Jin-Gyun CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3  pp. 694-697
Type of Manuscript: LETTER
Category: VLSI Design Technology and CAD
Keyword: 
digital arithmetic,  modified Booth multiplier,  predetermined coefficients, 
  Summary |  Full Text:PDF (175KB)
A Custom VLSI Architecture for the Solution of FDTD Equations
Pisana PLACIDI  Leonardo VERDUCCI  Guido MATRELLA  Luca ROSELLI  Paolo CIAMPOLINI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Vol. E85-C  No. 3  pp. 572-577
Type of Manuscript: Special Section PAPER (Special Issue on Signals, Systems and Electronics Technology)
Category: Circuit
Keyword: 
FDTD method,  digital arithmetic,  very-large scale integration,  VHDL language, 
  Summary |  Full Text:PDF (281.1KB)