Keyword : digital arithmetic


High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
Masamitsu TANAKA Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 703-709
Type of Manuscript:  Special Section PAPER (Special Section on Cutting-Edge Technologies of Superconducting Electronics)
Category: 
Keyword: 
digital arithmeticdigit-serial processinghardware algorithmrapid single-flux-quantum logicsigned-digit representationsystolic array
 Summary | Full Text:PDF(471.1KB)

High-Speed Operation of 0.25-mV RSFQ Arithmetic Logic Unit Based on 10-kA/cm2 Nb Process Technology
Masamitsu TANAKA Atsushi KITAYAMA Masakazu OKADA Tomohito KOUKETSU Takumi TAKINAMI Masato ITO Akira FUJIMAKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3 ; pp. 166-172
Type of Manuscript:  Special Section PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single-flux-quantum logiclow-powerlow-voltagedigital arithmetic
 Summary | Full Text:PDF(1.5MB)

Fixed-Width Group CSD Multiplier Design
Yong-Eun KIM Kyung-Ju CHO Jin-Gyun CHUNG Xinming HUANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/06/01
Vol. E93-D  No. 6 ; pp. 1497-1503
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
fixed-widthGCSD multiplierquantization errordigital arithmetic
 Summary | Full Text:PDF(582.8KB)

Low Power MAC Design with Variable Precision Support
Young-Geun LEE Han-Sam JUNG Ki-Seok CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/07/01
Vol. E92-A  No. 7 ; pp. 1623-1632
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
digital arithmeticdigital signal processorsconstant multiplicationpower consumption
 Summary | Full Text:PDF(1.6MB)

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients
Yong-Eun KIM Kyung-Ju CHO Jin-Gyun CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3 ; pp. 694-697
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
digital arithmeticmodified Booth multiplierpredetermined coefficients
 Summary | Full Text:PDF(174.2KB)

A Custom VLSI Architecture for the Solution of FDTD Equations
Pisana PLACIDI Leonardo VERDUCCI Guido MATRELLA Luca ROSELLI Paolo CIAMPOLINI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/03/01
Vol. E85-C  No. 3 ; pp. 572-577
Type of Manuscript:  Special Section PAPER (Special Issue on Signals, Systems and Electronics Technology)
Category: Circuit
Keyword: 
FDTD methoddigital arithmeticvery-large scale integrationVHDL language
 Summary | Full Text:PDF(279.1KB)