Keyword : design verification


Circuit Description and Design Flow of Superconducting SFQ Logic Circuits
Kazuyoshi TAKAGI Nobutaka KITO Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/03/01
Vol. E97-C  No. 3 ; pp. 149-156
Type of Manuscript:  INVITED PAPER (Special Section on Leading-Edge Technology of Superconductor Large-Scale Integrated Circuits)
Category: 
Keyword: 
single-flux-quantum circuitdesign methodologycircuit descriptionlogic designlayout designdesign verification
 Summary | Full Text:PDF(2.8MB)

Incremental CTL Model Checker for Fair States
Victor R. L. SHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/07/25
Vol. E82-D  No. 7 ; pp. 1126-1130
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
design verificationCTL model checkerfair states
 Summary | Full Text:PDF(288KB)

TPF: An Effective Method for Verifying Synchronous Circuits with Induction-Based Provers
Kazuko TAKAHASHI Hiroshi FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/01/25
Vol. E81-D  No. 1 ; pp. 12-18
Type of Manuscript:  PAPER
Category: Computer Hardware and Design
Keyword: 
design verificationhardware descriptionBoyer-Moore theorem proverautomated deductionsynchronous circuits
 Summary | Full Text:PDF(546.3KB)

Integrated Design and Test Assistance for Pipeline Controllers
Hiroaki IWASHITA Tsuneo NAKATA Fumiyasu HIROSE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 747-754
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
design verificationtest programVHDLRISC processor
 Summary | Full Text:PDF(600.3KB)

Formal Design Verification of Sequential Machines Based on Symbolic Model Checking for Branching Time Regular Temporal Logic
Kiyoharu HAMAGUCHI Hiromi HIRAISHI Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A  No. 10 ; pp. 1220-1229
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
design verificationsequential machinestemporal logicmodel checkingbinary decision diagram
 Summary | Full Text:PDF(786KB)