Keyword : design space exploration


Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path
Ittetsu TANIGUCHI Kohei AOKI Hiroyuki TOMIYAMA Praveen RAGHAVAN Francky CATTHOOR Masahiro FUKUI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/02/01
Vol. E97-A  No. 2 ; pp. 606-615
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design space explorationarchitecture explorationvery long instruction-set word (VLIW) processorgenetic algorithm (GA)
 Summary | Full Text:PDF(1.6MB)

Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design
Yuki ANDO Seiya SHIBATA Shinya HONDA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2509-2516
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
system-level designhardware sharingdesign space explorationMPSoC
 Summary | Full Text:PDF(1.4MB)

Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
Farhad MEHDIPOUR Hamid NOORI Koji INOUE Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3182-3192
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
reconfigurable instruction-set processoranalytical modelingdesign space explorationdata flow graph accelerator
 Summary | Full Text:PDF(1009.8KB)

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3258-3267
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
partial forwardinginstruction schedulingcompilerdesign space exploration
 Summary | Full Text:PDF(561.2KB)

A Two-Level Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3238-3247
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
two-level cacheL1/L2cache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF(522.3KB)

A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement
Liang-Bi CHEN Chi-Tsai YEH Hung-Yu CHEN Ing-Jer HUANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3193-3202
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
design space explorationsystem-on-a-chip (SoC)SystemCUML3D graphics
 Summary | Full Text:PDF(1MB)

An L1 Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1442-1453
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
cachecache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF(1.1MB)

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications
Jinhyun CHO Doowon LEE Sangyong YOON Sanggyu PARK Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/01/01
Vol. E92-A  No. 1 ; pp. 279-290
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SMPTE 421M-2006 VC-1video decodertransaction level modelingdesign space exploration
 Summary | Full Text:PDF(2.8MB)

Skeletons and Asynchronous RPC for Embedded Data and Task Parallel Image Processing
Wouter CAARLS Pieter JONKER Henk CORPORAAL 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2006/07/01
Vol. E89-D  No. 7 ; pp. 2036-2043
Type of Manuscript:  Special Section PAPER (Special Section on Machine Vision Applications)
Category: Parallel and Distributed Computing
Keyword: 
design space explorationheterogeneous architecturesconstrained architecturesalgorithmic skeletonsremote procedure callfuturesrun-time scheduling
 Summary | Full Text:PDF(295KB)

A Plan-Generation-Evaluation Framework for Design Space Exploration of Digital Systems Design
Jun Kyoung KIM Tag Gon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/03/01
Vol. E89-A  No. 3 ; pp. 772-781
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
design space explorationplan-generation-evaluation frameworkgraph pruningattributed AND-OR graph
 Summary | Full Text:PDF(1.9MB)

An Efficient Method for System-Level Exploration of Global Optimum in a Parameterized ASIP Design
Yeong-Geol KIM Tag-Gon KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3297-3302
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
design space explorationglobal optimizationparameterized ASIP
 Summary | Full Text:PDF(250.5KB)

A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
Shinsuke KOBAYASHI Kentaro MITA Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2586-2595
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Hardware/Software Codesign
Keyword: 
compiler generationASIPdesign space exploration
 Summary | Full Text:PDF(527.6KB)