Keyword : datapath


Arithmetic Circuit Verification Based on Symbolic Computer Algebra
Yuki WATANABE Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/10/01
Vol. E91-A  No. 10 ; pp. 3038-3046
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
datapatharithmetic circuitsformal verificationcomputer algebra
 Summary | Full Text:PDF(754.8KB)

A Power Reduction Scheme for Data Buses by Dynamic Detection of Active Bits
Masanori MUROYAMA Akihiko HYODO Takanori OKUMA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 598-605
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
active bitlow powerdatapathdata busdynamic
 Summary | Full Text:PDF(421.1KB)

Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms
Jun SAKIYAMA Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3009-3019
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
computer arithmetic algorithmsparallel countersmultipliersdatapathVLSIcircuit synthesis
 Summary | Full Text:PDF(905.4KB)

Architecture Evaluation Based on the Datapath Structure and Parallel Constraint
Masayuki YAMAGUCHI Akihisa YAMADA Toshihiro NAKAOKA Takashi KAMBE Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1853-1860
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
performance evaluationdatapathstructureparallel constraint
 Summary | Full Text:PDF(751.3KB)