Keyword : constraint graph


Fujimaki-Takahashi Squeeze: Linear Time Construction of Constraint Graphs of Floorplan for a Given Permutation
Toshihiko TAKAHASHI Ryo FUJIMAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1071-1076
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
floorplanrepresentationpermutationconstraint graph
 Summary | Full Text:PDF(207.8KB)

Checking of Timing Constraint Violation Based on Graph in Reactive Systems
Hiromi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 909-913
Type of Manuscript:  LETTER
Category: Graphs and Networks
Keyword: 
timing constraint violationconstraint graphReal Time LogicFloyd-Warshall algorithm
 Summary | Full Text:PDF(251.4KB)

Procedural Detailed Compaction for the Symbolic Layout Design of CMOS Leaf Cells
Hiroshi MIYASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/11/25
Vol. E77-A  No. 11 ; pp. 1957-1969
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
symbolic layoutcompactiondesign ruleleaf cellconstraint graph
 Summary | Full Text:PDF(1.1MB)

A preconstrained Compaction Method Applied to Direct Design-Rule Conversion of CMOS Layouts
Hiroshi MIYASHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/10/25
Vol. E77-A  No. 10 ; pp. 1684-1691
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
compactiondesign rulesconstraint graphstrongly-connected-componentscell layouts
 Summary | Full Text:PDF(806.4KB)