Keyword : compiler


An Integrated Framework for Energy Optimization of Embedded Real-Time Applications
Hideki TAKASE Gang ZENG Lovic GAUTHIER Hirotaka KAWASHIMA Noritoshi ATSUMI Tomohiro TATEMATSU Yoshitake KOBAYASHI Takenori KOSHIRO Tohru ISHIHARA Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2477-2487
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
energy optimizationcompilerprofilerreal-time operating systemsembedded systems
 Summary | Full Text:PDF(7.3MB)

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design
Hiroshi NAKAMURA Weihan WANG Yuya OHTA Kimiyoshi USAMI Hideharu AMANO Masaaki KONDO Mitaro NAMIKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/04/01
Vol. E96-C  No. 4 ; pp. 404-412
Type of Manuscript:  INVITED PAPER (Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
low-power circuit techniquesfine grained power-gatingcompilersystem hierarchy cooperation
 Summary | Full Text:PDF(3.1MB)

DiSCo: Distributed Scalable Compilation Tool for Heavy Compilation Workload
Kyongjin JO Seon Wook KIM Jong-Kook KIM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/03/01
Vol. E96-D  No. 3 ; pp. 589-600
Type of Manuscript:  PAPER
Category: Fundamentals of Information Systems
Keyword: 
distributed compilerremote linkingcompiler
 Summary | Full Text:PDF(1.9MB)

Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems
Hideki TAKASE Hiroyuki TOMIYAMA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/10/01
Vol. E94-A  No. 10 ; pp. 1954-1964
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
scratch-pad memoryenergy optimizationcompilercode allocationmulti-task systems
 Summary | Full Text:PDF(1.1MB)

A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System
Min ZHU Leibo LIU Shouyi YIN Chongyong YIN Shaojun WEI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12 ; pp. 3202-3210
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: 
Keyword: 
SimREMUSsimulatorreconfigurable multimedia systemcompilerdebugger
 Summary | Full Text:PDF(1.6MB)

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor
Takuji HIEDA Hiroaki TANAKA Keishi SAKANUSHI Yoshinori TAKEUCHI Masaharu IMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3258-3267
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
partial forwardinginstruction schedulingcompilerdesign space exploration
 Summary | Full Text:PDF(561.2KB)

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram
Hiroaki TANAKA Yoshinori TAKEUCHI Keishi SAKANUSHI Masaharu IMAI Hiroki TAGAWA Yutaka OTA Nobu MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2800-2809
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
compilerSIMD instructionsmulti-valued decision diagram
 Summary | Full Text:PDF(555.8KB)

Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation
Takefumi MIYOSHI Nobuhiko SUGINO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/12/01
Vol. E90-D  No. 12 ; pp. 1967-1976
Type of Manuscript:  Special Section PAPER (Special Section on Reconfigurable Systems)
Category: Reconfigurable Device and Design Tools
Keyword: 
dynamic reconfigurable processorcompilerautomatic context generation
 Summary | Full Text:PDF(698.6KB)

Loop and Address Code Optimization for Digital Signal Processors
Jong-Yeol LEE In-Cheol PARK 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/06/01
Vol. E85-A  No. 6 ; pp. 1408-1415
Type of Manuscript:  LETTER
Category: Digital Signal Processing
Keyword: 
digital signal processor (DSP)compilercode optimization
 Summary | Full Text:PDF(466.7KB)

Hardware Synthesis from C Programs with Estimation of Bit Length of Variables
Osamu OGAWA Kazuyoshi TAKAGI Yasufumi ITOH Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2338-2346
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level synthesishardware/software codesignVHDLC languagecompiler
 Summary | Full Text:PDF(724.5KB)

An Analysis for Fast Construction of States in the Bottom-Up Tree Pattern Matching Scheme
Kyung-Woo KANG Kwang-Moo CHOE Min-Soo JUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/05/25
Vol. E82-D  No. 5 ; pp. 973-976
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
compilercode generator generatortree grammardynamic programming
 Summary | Full Text:PDF(358.2KB)

A VLIW Geometry Processor with Software Bypass Mechanism
Yasunori KIMURA Akira ASATO Toshihiro OZAWA Hiroshi NAKAYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 669-679
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
3D graphicsgeometry processingVLIWcompiler
 Summary | Full Text:PDF(980.6KB)

DSP Code Optimization Methods Utilizing Addressing Operations at the Codes without Memory Accesses
Nobuhiko SUGINO Hironobu MIYAZAKI Akinori NISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Vol. E80-A  No. 12 ; pp. 2562-2571
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
digital signal processorcompilercode optimizationmemory addressing
 Summary | Full Text:PDF(782.1KB)

Peephole Optimizer in Retargetable Compilers*
Tzer-Shyong CHEN Feipei LAI Shu-Lin HWANG Rung-Ji SHANG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/09/25
Vol. E79-D  No. 9 ; pp. 1248-1256
Type of Manuscript:  PAPER
Category: Sofware System
Keyword: 
code generatorcompilerpeephole optimizerretargetable compiler
 Summary | Full Text:PDF(823.3KB)

Eliminating Unnecessary Items from the One-Pass Evaluation of Attribute Grammars
Yoshimichi WATANABE Takehiro TOKUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4 ; pp. 312-320
Type of Manuscript:  PAPER
Category: Software Theory
Keyword: 
attribute grammarcompilerformal language
 Summary | Full Text:PDF(680.1KB)