Keyword : combinational circuit


Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits
Masaki HASHIZUME Hiroyuki YOTSUYANAGI Takeomi TAMESADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 571-579
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Fault Detection
Keyword: 
feedback bridging faultcombinational circuitlogical oscillation
 Summary | Full Text:PDF(564KB)

Diagnosing Delay Faults in Combinational Circuits Under the Ambiguous Delay Model
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/12/25
Vol. E82-D  No. 12 ; pp. 1563-1571
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitambiguous delay modelmultiple fault diagnosispath-tracing method
 Summary | Full Text:PDF(659.1KB)

A Method of Generating Tests with Linearity Property for Gate Delay Faults in Combinational Circuits
Hiroshi TAKAHASHI Kwame Osei BOATENG Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1999/11/25
Vol. E82-D  No. 11 ; pp. 1466-1473
Type of Manuscript:  PAPER
Category: Fault Tolerant Computing
Keyword: 
combinational circuitmarginal chipgate delay faulttest generationtest with linearity property
 Summary | Full Text:PDF(598KB)

Multiple Gate Delay Fault Diagnosis Using Test-Pairs for Marginal Delays
Kwame Osei BOATENG Hiroshi TAKAHASHI Yuzo TAKAMATSU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D  No. 7 ; pp. 706-715
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Fault Diagnosis
Keyword: 
combinational circuitfault diagnosismultiple delay faultdiagnostic rulespath-tracing methodtest-pairs for marginal delays
 Summary | Full Text:PDF(814.1KB)

Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses
Kazuyoshi TAKAGI Koyo NITTA Hironori BOUNO Yasuhiko TAKENAGA Shuzo YAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/04/25
Vol. E80-A  No. 4 ; pp. 663-669
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
computational complexityBoolean functionordered binary decision diagramsatisfiabilitycombinational circuitcutwidthsum-of-product formzero-suppressed binary decision diagrams (BDD)ternary decision diagram
 Summary | Full Text:PDF(675.4KB)

A Single Bridging Fault Location Technique for CMOS Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 817-821
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
fault diagnosisbridging faultCMOScombinational circuit
 Summary | Full Text:PDF(398KB)

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis
Seiji KAJIHARA Rikiya NISHIGAYA Tetsuji SUMIOKA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/07/25
Vol. E78-D  No. 7 ; pp. 811-816
Type of Manuscript:  Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems)
Category: 
Keyword: 
test generationmultiple stuck-at faultvector pair analysiscombinational circuit
 Summary | Full Text:PDF(593KB)

An Efficient Fault Simulation Method for Reconvergent Fan-Out Stem
Sang Seol LEE Kyu Ho PARK 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 771-775
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault simulationreconvergent fan-out stemcombinational circuitprimary stem regionexit line
 Summary | Full Text:PDF(376KB)

SIFLAP-G: A Method of Diagnosing Gate-Level Faults in Combinational Circuits
Koji YAMAZAKI Teruhiko YAMADA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1993/07/25
Vol. E76-D  No. 7 ; pp. 826-831
Type of Manuscript:  Special Section PAPER (Special Issue on VLSI Testing and Testable Design)
Category: 
Keyword: 
fault diagnosisgate-level faultcombinational circuitprobing
 Summary | Full Text:PDF(455.2KB)