Keyword : clock


Network Clock System that Ensures a High Level of Frequency Accuracy
Shuichi FUJIKAWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2015/11/01
Vol. E98-B  No. 11 ; pp. 2212-2226
Type of Manuscript:  PAPER
Category: Transmission Systems and Transmission Equipment for Communications
Keyword: 
clocksynchronizationevaluationalgorithmMTIEGPS
 Summary | Full Text:PDF(2.7MB)

Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array
Tadayoshi ENOMOTO Suguru NAGAYAMA Hiroaki SHIKANO Yousuke HAGIWARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/04/01
Vol. E91-C  No. 4 ; pp. 553-561
Type of Manuscript:  Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
Category: 
Keyword: 
power dissipationCMOSclockregister
 Summary | Full Text:PDF(1.4MB)

CMOS Level Converter with Balanced Rise and Fall Delays
Min-su KIM Young-Hyun JUN Sung-Bae PARK Bai-Sun KONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/01/01
Vol. E90-C  No. 1 ; pp. 192-195
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
level convertervoltage scalingclocklow power
 Summary | Full Text:PDF(1.4MB)

Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core
Tetsuya YAMADA Masahide ABE Yusuke NITTA Kenji OGURA Manabu KUSAOKE Makoto ISHIKAWA Motokazu OZAWA Kiwamu TAKADA Fumio ARAKAWA Osamu NISHII Toshihiro HATTORI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 287-294
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: Low Power Techniques
Keyword: 
embedded processorclockgated clockflip-flop
 Summary | Full Text:PDF(1.4MB)

Efficient Routing of Board-Level Optical Clocks for Ultra High-Speed Systems
Chung-Seok (Andy) SEO Abhijit CHATTERJEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/06/01
Vol. E87-A  No. 6 ; pp. 1310-1317
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2003))
Category: 
Keyword: 
clockoptical waveguideinterconnectphysical designoptimization
 Summary | Full Text:PDF(1.2MB)

A 0.25 µm CMOS/SIMOX PLL Clock Generator Embedded in a Gate Array LSI with a Locking Range of 5 to 500 MHz
Hiroki SUTOH Kimihiro YAMAKOSHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/07/25
Vol. E82-C  No. 7 ; pp. 1334-1340
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLLCMOS/SIMOXVCOclockjitterskewlock range
 Summary | Full Text:PDF(2MB)

111-MHz 1-Mbit CMOS Synchronous Burst SRAM Using a Clock Activation Control Method
Hirotoshi SATO Shigeki OHBAYASHI Yasuyuki OKAMOTO Setsu KONDOH Tomohisa WADA Ryuuichi MATSUO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 735-742
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
memorysynchronous SRAMhigh speed SRAM, low powerclock
 Summary | Full Text:PDF(823.7KB)