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Keyword : clock skew

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits Kazuyoshi TAKAGI Yuki ITO Shota TAKESHIMA Masamitsu TANAKA Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/03/01 Vol. E94-C No. 3 pp. 288-295 Type of Manuscript: Special Section PAPER (Special Section on Superconducting Signal Processing Technologies) Category: Keyword: single-flux-quantum circuit, design methodology, clock tree synthesis, clock skew,
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A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits Koji OBATA Kazuyoshi TAKAGI Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3772-3782 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: clock scheduling, clock skew, micropipeline, RSFQ,
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Clock Skew Evaluation Considering Manufacturing Variability in Mesh-Style Clock Distribution Shinya ABE Masanori HASHIMOTO Takao ONOYE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/12/01 Vol. E91-A No. 12 pp. 3481-3487 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Device and Circuit Modeling and Analysis Keyword: mesh-style clock distribution, clock skew,
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Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution Akira UTAGAWA Tetsuya ASAI Tetsuya HIROSE Yoshihito AMEMIYA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/09/01 Vol. E91-A No. 9 pp. 2475-2481 Type of Manuscript: Special Section PAPER (Special Section on Nonlinear Theory and its Applications) Category: Electronic Circuits and Systems Keyword: clock distribution, synchronization, nonlinear oscillators, clock skew,
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Variant X-Tree Clock Distribution Network and Its Performance Evaluations Xu ZHANG Xiaohong JIANG Susumu HORIGUCHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2007/10/01 Vol. E90-C No. 10 pp. 1909-1918 Type of Manuscript: Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market) Category: Low-Power and High-Performance VLSI Circuit Technology Keyword: clock distribution network (CDN), Variant X-Tree, X Architecture, H-Tree, clock skew,
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Simultaneous Compensation of RC Mismatch and Clock Skew in Time-Interleaved S/H Circuits Zheng LIU Masanori FURUTA Shoji KAWAHITO
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/06/01 Vol. E89-C No. 6 pp. 710-716 Type of Manuscript: Special Section PAPER (Special Section on Analog Circuit and Device Technologies) Category: Keyword: RC mismatch, clock skew, time-interleaved ADCs, compensation, sampling clock phase calibration,
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Statistical Analysis of Clock Skew Variation in H-Tree Structure Masanori HASHIMOTO Tomonori YAMAMOTO Hidetoshi ONODERA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3375-3381 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: clock skew, manufacturing variability, environmental variability, transition time constraint, statistical analysis, clock distribution,
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On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design Takashi SATO Junji ICHIMIYA Nobuto ONO Koutaro HACHIYA Masanori HASHIMOTO
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2005/12/01 Vol. E88-A No. 12 pp. 3382-3389 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Prediction and Analysis Keyword: thermal simulation, thermal gradient, temperature flattening, clock skew, reliability, timing,
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Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor Hidehiro TAKATA Rei AKIYAMA Tadao YAMANAKA Haruyuki OHKUMA Yasue SUETSUGU Toshihiro KANAOKA Satoshi KUMAKI Kazuya ISHIHARA Atsuo HANAMI Tetsuya MATSUMURA Tetsuya WATANABE Yoshihide AJIOKA Yoshio MATSUDA Syuhei IWADE
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2002/02/01 Vol. E85-C No. 2 pp. 368-374 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors) Category: Product Designs Keyword: multimedia processor, clock skew, cross-talk noise, IR drop, MPEG-2 encoder,
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Statistical Skew Modeling and Clock Period Optimization of Wafer Scale H-Tree Clock Distribution Network Xiaohong JIANG Susumu HORIGUCHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/11/01 Vol. E84-D No. 11 pp. 1476-1485 Type of Manuscript: Special Section PAPER (Special Issue on Function Integrated Information Systems) Category: Keyword: H-tree, clock skew, clock delay, clock period, process variations,
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A Clock Distribution Technique with an Automatic Skew Compensation Circuit Hiroki SUTOH Kimihiro YAMAKOSHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1998/02/20 Vol. E81-C No. 2 pp. 277-283 Type of Manuscript: PAPER Category: Integrated Electronics Keyword: clock skew, clock distribution, compensation, variable delay line, CMOS,
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A Balanced-Mesh Clock Routing Technique for Performance Improvement Hidenori SATO Hiroaki MATSUDA Akira ONOZAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1997/08/20 Vol. E80-A No. 8 pp. 1489-1495 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: LSI, CAD, layout design, clock skew, partitioning, routing, MPEG2,
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