Keyword : cache


Cache Effect of Shared DNS Resolver
Kazunori FUJIWARA Akira SATO Kenichi YOSHIDA 
Publication:   
Publication Date: 2019/06/01
Vol. E102-B  No. 6 ; pp. 1170-1179
Type of Manuscript:  PAPER
Category: Internet
Keyword: 
DNScache
 Summary | Full Text:PDF(1.5MB)

A Hardware-Based Caching System on FPGA NIC for Blockchain
Yuma SAKAKIBARA Shin MORISHIMA Kohei NAKAMURA Hiroki MATSUTANI 
Publication:   
Publication Date: 2018/05/01
Vol. E101-D  No. 5 ; pp. 1350-1360
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
BlockchainIoTFPGAcache
 Summary | Full Text:PDF(5.2MB)

Content Retrieval Method in Cooperation with CDN and Breadcrumbs-Based In-Network Guidance Method
Yutaro INABA Yosuke TANIGAWA Hideki TODE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2016/05/01
Vol. E99-B  No. 5 ; pp. 992-1001
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architectures and Management Methods that Enable Flexible and Secure Deployment of Network Services)
Category: 
Keyword: 
Breadcrumbscachecontent-oriented networkBreadcrumbs+
 Summary | Full Text:PDF(844.2KB)

A Light-Weight Rollback Mechanism for Testing Kernel Variants in Auto-Tuning
Shoichi HIRASAWA Hiroyuki TAKIZAWA Hiroaki KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/12/01
Vol. E98-D  No. 12 ; pp. 2178-2186
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Software
Keyword: 
auto-tuningrollbackcacheearly termination
 Summary | Full Text:PDF(656.3KB)

Cache-Conscious Data Access for DBMS in Multicore Environments
Fang XI Takeshi MISHIMA Haruo YOKOTA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2015/05/01
Vol. E98-D  No. 5 ; pp. 1001-1012
Type of Manuscript:  Special Section PAPER (Special Section on Data Engineering and Information Management)
Category: 
Keyword: 
multicoreOLTPmiddlewarecache
 Summary | Full Text:PDF(4MB)

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation
Yohei NAKATA Yuta KIMI Shunsuke OKUMURA Jinwook JUNG Takuya SAWADA Taku TOSHIKAWA Makoto NAGATA Hirofumi NAKANO Makoto YABUUCHI Hidehiro FUJIWARA Koji NII Hiroyuki KAWAI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2014/04/01
Vol. E97-C  No. 4 ; pp. 332-341
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
design for robustnesscachevariation tolerance7T/14T SRAM
 Summary | Full Text:PDF(4.6MB)

Region-Based Way-Partitioning on L1 Data Cache for Low Power
Zhong ZHENG Zhiying WANG Li SHEN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2013/11/01
Vol. E96-D  No. 11 ; pp. 2466-2469
Type of Manuscript:  LETTER
Category: Computer System
Keyword: 
cachelow powerregion-basedway-partitioning
 Summary | Full Text:PDF(506.9KB)

Active Breadcrumbs: Adaptive Distribution of In-Network Guidance Information for Content-Oriented Networks
Masayuki KAKIDA Yosuke TANIGAWA Hideki TODE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2013/07/01
Vol. E96-B  No. 7 ; pp. 1670-1679
Type of Manuscript:  Special Section PAPER (Special Section on Internet Architectures, Protocols, and Management Methods that Enable Sustainable Development)
Category: 
Keyword: 
Breadcrumbscachecontent-oriented networkBreadcrumbs+Active Breadcrumbs
 Summary | Full Text:PDF(919.4KB)

Bayesian Theory Based Adaptive Proximity Data Accessing for CMP Caches
Guohong LI Zhenyu LIU Sanchuan GUO Dongsheng WANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/06/01
Vol. E96-A  No. 6 ; pp. 1293-1305
Type of Manuscript:  Special Section PAPER (Special Section on Circuit, System, and Computer Technologies)
Category: 
Keyword: 
Bayesian Decisioncachemulticore
 Summary | Full Text:PDF(2.5MB)

Evaluation of a New Power-Gating Scheme Utilizing Data Retentiveness on Caches
Kyundong KIM Seidai TAKEDA Shinobu MIWA Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2012/12/01
Vol. E95-A  No. 12 ; pp. 2301-2308
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
low-powercacheleakage power
 Summary | Full Text:PDF(1.6MB)

Using Cacheline Reuse Characteristics for Prefetcher Throttling
Hidetsugu IRIE Takefumi MIYOSHI Goki HONJO Kei HIRAKI Tsutomu YOSHINAGA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2012/12/01
Vol. E95-D  No. 12 ; pp. 2928-2938
Type of Manuscript:  Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category: Computer Architecture
Keyword: 
microarchitecturecacheprefetch
 Summary | Full Text:PDF(1.6MB)

An L1 Cache Design Space Exploration System for Embedded Applications
Nobuaki TOJO Nozomu TOGAWA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1442-1453
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
cachecache optimizationdesign space explorationcache simulationembedded system
 Summary | Full Text:PDF(1.1MB)

Cache Optimization for H.264/AVC Motion Compensation
Sangyong YOON Soo-Ik CHAE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2008/12/01
Vol. E91-D  No. 12 ; pp. 2902-2905
Type of Manuscript:  LETTER
Category: Image Processing and Video Processing
Keyword: 
cacheH.264motion compensationmemory bandwidthDDR SDRAM
 Summary | Full Text:PDF(679.7KB)

Way-Scaling to Reduce Power of Cache with Delay Variation
Maziar GOUDARZI Tadayuki MATSUMURA Tohru ISHIHARA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3576-3584
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
leakagepower reductioncachewithin-die variationdelay variationway scaling
 Summary | Full Text:PDF(1.3MB)

Cache Efficient Radix Sort for String Sorting
Waihong NG Katsuhiko KAKEHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/02/01
Vol. E90-A  No. 2 ; pp. 457-466
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
radix sortsortingcachestring sortinghigh performance
 Summary | Full Text:PDF(615KB)

Return Address Protection on Cache Memories
Koji INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/12/01
Vol. E89-C  No. 12 ; pp. 1937-1947
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
low energysecuritycachebuffer overflowstack smashing
 Summary | Full Text:PDF(1.6MB)

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic
Michitaka OKUNO Shinji NISHIMURA Shin-ichi ISHIDA Hiroaki NISHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1620-1628
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
100-Gbps Ethernetnetwork processorcachenetwork trafficlow power
 Summary | Full Text:PDF(1.7MB)

Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy
Hidekazu TANAKA Koji INOUE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3274-3281
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Low Power Methodology
Keyword: 
low powercacheway predictionconfidence information
 Summary | Full Text:PDF(1MB)

Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches
Reiko KOMIYA Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/04/01
Vol. E88-A  No. 4 ; pp. 862-868
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low powercacheleakage
 Summary | Full Text:PDF(1014.7KB)

Design and Evaluation of a High Speed Routing Lookup Architecture
Jun ZHANG JeoungChill SHIM Hiroyuki KURINO Mitsumasa KOYANAGI 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2004/03/01
Vol. E87-B  No. 3 ; pp. 406-412
Type of Manuscript:  Special Section PAPER (Special Section on Internet Technology IV)
Category: Implementation and Operation
Keyword: 
IP routingselective binary search algorithmpipelined architecturecache
 Summary | Full Text:PDF(1.2MB)

Reducing Memory System Energy by Software-Controlled On-Chip Memory
Masaaki KONDO Hiroshi NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 580-588
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Architecture and Algorithms
Keyword: 
processor architecturecacheon-chip memoryway activationmemory traffic
 Summary | Full Text:PDF(886.6KB)

A Randomized Online Algorithm for the File Caching Problem
Seiichiro TANI Toshiaki MIYAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2003/04/01
Vol. E86-D  No. 4 ; pp. 686-697
Type of Manuscript:  PAPER
Category: Algorithms
Keyword: 
networkcachecompetitiveonline algorithm
 Summary | Full Text:PDF(1003.2KB)

Trends in High-Performance, Low-Power Cache Memory Architectures
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 304-314
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: High-Performance Technologies
Keyword: 
cachelow powerhigh performancemicroprocessorsurvey
 Summary | Full Text:PDF(238.5KB)

Omitting Cache Look-up for High-Performance, Low-Power Microprocessors
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/02/01
Vol. E85-C  No. 2 ; pp. 279-287
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
Category: Low-Power Technologies
Keyword: 
cachelow powerlook uprun time
 Summary | Full Text:PDF(726.5KB)

Reducing Cache Energy Dissipation by Using Dual Voltage Supply
Vasily G. MOSHNYAGA Hiroshi TSUJI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2762-2768
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Optimization of Power and Timing
Keyword: 
cacheprocessor architecturelow-power
 Summary | Full Text:PDF(478.8KB)

A Design Framework for Online Algorithms Solving the Object Replacement Problem
Seiichiro TANI Toshiaki MIYAZAKI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2001/09/01
Vol. E84-D  No. 9 ; pp. 1135-1143
Type of Manuscript:  PAPER
Category: Algorithms
Keyword: 
networkcachecompetitiveonline algorithm
 Summary | Full Text:PDF(457.4KB)

Exploiting Metadata of Absent Objects for Proxy Cache Consistency
Jooyong KIM Hyokyung BAHN Kern KOH 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2001/05/01
Vol. E84-B  No. 5 ; pp. 1406-1412
Type of Manuscript:  PAPER
Category: Network
Keyword: 
proxycacheconsistencymetadataWorld Wide Web
 Summary | Full Text:PDF(222.1KB)

Area-Efficient Multi-Port SRAMs for On-Chip Data-Storage with High Random-Access Bandwidth and Large Storage Capacity
Hans Jurgen MATTAUSCH Koji KISHI Takayuki GYOHTEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 410-417
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
multiple-portsSRAMcacheaccess bandwidth
 Summary | Full Text:PDF(7.7MB)

A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1716-1723
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
cachelow powervariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1001.2KB)

Evaluation of Compulsory Miss Ratio for Address Cache and Replacement Policies for Restoring Packet Reachability
Masaki AIDA Noriyuki TAKAHASHI Michiyo MATSUDA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2000/07/25
Vol. E83-B  No. 7 ; pp. 1400-1408
Type of Manuscript:  PAPER
Category: Fiber-Optic Transmission
Keyword: 
HTTPcachedual Zipfian modelcompulsory misspurge
 Summary | Full Text:PDF(861.6KB)

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/05/25
Vol. E83-D  No. 5 ; pp. 1048-1057
Type of Manuscript:  PAPER
Category: Computer System Element
Keyword: 
cachevariable line-sizemerged DRAM/logic LSIshigh bandwidth
 Summary | Full Text:PDF(1015.7KB)

A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
Koji INOUE Tohru ISHIHARA Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/02/25
Vol. E83-C  No. 2 ; pp. 186-194
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
Category: 
Keyword: 
cachelow powerlow energyway predictionhigh performance
 Summary | Full Text:PDF(1015.4KB)

A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
Kenichi OSADA Hisayuki HIGUCHI Koichiro ISHIBASHI Naotaka HASHIMOTO Kenji SHIOZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/01/25
Vol. E83-C  No. 1 ; pp. 109-114
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
cacheSRAMlow powertwo-portmicroprocessor
 Summary | Full Text:PDF(1.4MB)

Hash-Based Query Caching Method for Distributed Web Caching in Wide Area Networks
Takuya ASAKA Hiroyoshi MIWA Yoshiaki TANAKA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1999/06/25
Vol. E82-B  No. 6 ; pp. 907-914
Type of Manuscript:  Special Section PAPER (Special Issue on Distributed Processing for Controlling Telecommunications Systems)
Category: 
Keyword: 
Webcachequeryhash
 Summary | Full Text:PDF(470.6KB)

Planning and Design of Contents-Delivery Systems Using Satellite and Terrestrial Networks
Kenichi MASE Takuya ASAKA Yoshiaki TANAKA Hideyoshi TOMINAGA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/11/25
Vol. E81-B  No. 11 ; pp. 2041-2047
Type of Manuscript:  Special Section PAPER (Special Issue on Performance and Quality of Service (QoS) of Multimedia Networks)
Category: Satellite and Wireless Networks
Keyword: 
satelliteinternetcachecontentscostbroadcast
 Summary | Full Text:PDF(645.2KB)

Query Caching Method for Distributed Web Caching
Takuya ASAKA Hiroyoshi MIWA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/10/25
Vol. E81-B  No. 10 ; pp. 1931-1935
Type of Manuscript:  LETTER
Category: Communication Networks and Services
Keyword: 
WWWcachequery messagequery relationship digraph
 Summary | Full Text:PDF(392.4KB)

High Bandwidth, Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs
Koji INOUE Koji KAI Kazuaki MURAKAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1438-1447
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
cachemerged DRAM/logic LSIsmemory system
 Summary | Full Text:PDF(938.1KB)

A Proposal of Dual Zipfian Model for Describing HTTP Access Trends and Its Application to Address Cache Design
Masaki AIDA Noriyuki TAKAHASHI Tetsuya ABE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1998/07/25
Vol. E81-B  No. 7 ; pp. 1475-1485
Type of Manuscript:  PAPER
Category: Communication Software
Keyword: 
data networkaddress resolutionZipf's lawcacheHTTPWWW
 Summary | Full Text:PDF(766.3KB)

SEWD: A Cache Architecture to Speed up the Misaligned Instruction Prefetch
Joon-Seo YIM In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/07/25
Vol. E80-D  No. 7 ; pp. 742-745
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
cachemicroprocessorpipeline
 Summary | Full Text:PDF(303.7KB)

Performance Evaluation of VEEC: The Virtual Execution Environment Control for a Remote Knowledge Base Access
Yoshitaka FUJIWARA Shin-ichiro OKADA Hiroyuki TAKADOI Toshiharu MATSUNISHI Hiroshi OHKAMA 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 1997/01/25
Vol. E80-B  No. 1 ; pp. 81-86
Type of Manuscript:  Special Section PAPER (Special Issue on Advances in Satellite Communications toward Multimedia Era)
Category: Protocol
Keyword: 
client-server systemknowledge basecachesatellite communicationsVSAT
 Summary | Full Text:PDF(650.2KB)

High-Speed CMOS SRAM Technologies for Cache Applications
Koichiro ISHIBASHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 724-734
Type of Manuscript:  INVITED PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
CMOS SRAMcachewave-pipelinedsense amplifierlow-voltage
 Summary | Full Text:PDF(1017.9KB)

A Supplementary Scheme for Reducing Cache Access Time
Jong-Hong BAE Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1996/04/25
Vol. E79-D  No. 4 ; pp. 385-387
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
computer architecturecachepenalty cyclespipeline
 Summary | Full Text:PDF(238.1KB)

A Selective Invalidation Strategy for Cache Coherence
Cosimo Antonio PRETE Gianpaolo PRINA Luigi RICCIARDI 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1995/10/25
Vol. E78-D  No. 10 ; pp. 1316-1320
Type of Manuscript:  LETTER
Category: Computer Hardware and Design
Keyword: 
cachecoherence protocolmultiprocessor
 Summary | Full Text:PDF(322.5KB)

A Cache-Coherent, Distributed Memory Multiprocessor System and Its Performance Analysis
Douglas E. MARQUARDT Hasan S. ALKHATIB 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1992/05/25
Vol. E75-D  No. 3 ; pp. 274-290
Type of Manuscript:  PAPER
Category: Computer Systems
Keyword: 
cachecache coherencymulticache consistencymultiprocessorperformance evaluation
 Summary | Full Text:PDF(1.4MB)