IEICE SEARCH SYSTEM

Keyword : cache memory

Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI Yuji KUNITAKE Toshinori SATO Hiroto YASUURA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2011/04/01 Vol. E94-C No. 4 pp. 520-529 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration) Category: Keyword: NBTI, SRAM, static noise margin, stress probability, register file, cache memory,
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Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems Hamid NOORI Maziar GOUDARZI Koji INOUE Kazuaki MURAKAMI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2008/04/01 Vol. E91-C No. 4 pp. 418-431 Type of Manuscript: Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories) Category: Keyword: temperature-aware design, cache memory, leakage current, low energy, embedded systems,
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Address Addition and Decoding without Carry Propagation Yung-Hei LEE Seung Ho HWANG
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1997/01/20 Vol. E80-D No. 1 pp. 98-100 Type of Manuscript: LETTER Category: Algorithm and Computational Complexity Keyword: decoding, cache memory, memory latency, pipelined architecture, parallel adders, carry propagation,
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An 8-mW, 8-kB Cache Memory Using an Automatic-Power-Save Architecture for Low Power RISC Microprocessors Yasuhisa SHIMAZAKI Katsuhiro NORISUE Koichiro ISHIBASHI Hideo MAEJIMA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1996/12/20 Vol. E79-C No. 12 pp. 1693-1698 Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies) Category: Keyword: RISC microprocessor, cache memory, low power,
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Hiding Data Cache Latency with Load Address Prediction Toshinori SATO Hiroshige FUJII Seigo SUZUKI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1996/11/20 Vol. E79-D No. 11 pp. 1523-1532 Type of Manuscript: PAPER Category: Computer Systems Keyword: RISC, cache memory, load-use hazard, load latency, address prediction,
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