Keyword : buffer insertion


Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming
Qing DONG Bo YANG Jing LI Shigetoshi NAKATAKE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3103-3110
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verfication
Keyword: 
placementfloorplanbuffer insertionmodule resizinggeometric programming
 Summary | Full Text:PDF(337.1KB)

Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
Yanming JIA Yici CAI Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3783-3792
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSIbuffer insertionphysical designDFMdummy fill
 Summary | Full Text:PDF(373.2KB)

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration
Yibo WANG Yici CAI Xianlong HONG Yi ZOU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5 ; pp. 1028-1037
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
interconnect optimizationaccurate delay modellow powerbuffer insertion
 Summary | Full Text:PDF(353.7KB)

Zero-Skew Driven Buffered RLC Clock Tree Construction
Jan-Ou WU Chia-Chun TSAI Chung-Chieh KUO Trong-Yen LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/03/01
Vol. E90-A  No. 3 ; pp. 651-658
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
clock treeupward propagationbuffer insertionzero skewSoC
 Summary | Full Text:PDF(1.3MB)

An Enhanced BSA for Floorplanning
Jyh Perng FANG Yang-Shan TONG Sao Jie CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/02/01
Vol. E89-A  No. 2 ; pp. 528-534
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
floorplanningbuffer insertionroutingdominant wide bus
 Summary | Full Text:PDF(349.5KB)

Timing-Driven Global Routing with Efficient Buffer Insertion
Jingyu XU Xianlong HONG Tong JING 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/11/01
Vol. E88-A  No. 11 ; pp. 3188-3195
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSI layoutglobal routingtiming-drivenbuffer insertionroutability
 Summary | Full Text:PDF(220.3KB)

A Performance-Driven Floorplanning Method with Interconnect Performance Estimation
Shinya YAMASAKI Shingo NAKAYA Shin'ichi WAKABAYASHI Tetsushi KOIDE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2775-2784
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
floorplanningtiming-driven layoutbuffer insertionwire sizingsimulated annealing
 Summary | Full Text:PDF(389KB)

Concurrent Gate Re-Sizing and Buffer Insertion to Reduce Glitch Power in CMOS Digital Circuit Design
Sungjae KIM Hyungwoo LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/01/01
Vol. E85-A  No. 1 ; pp. 234-240
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
low powerglitchgate sizingbuffer insertion
 Summary | Full Text:PDF(1.6MB)

A Post-Layout Optimization by Combining Buffer Insertion and Transistor Sizing
Sungkun LEE Juho KIM 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/10/01
Vol. E84-A  No. 10 ; pp. 2553-2560
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
buffer insertiontransistor sizingoptimization
 Summary | Full Text:PDF(741.1KB)