Keyword List
Japanese Page
SITE TOP
Login
To browse Full-Text PDF.
>
Forgotten your password?
Menu
Search
Full-Text Search
Search(JPN)
Latest Issue
A Fundamentals
Trans.Fundamentals.
JPN Edition(in Japanese)
B Communications
Trans.Commun.
JPN Edition(in Japanese)
C Electronics
Trans.Electron.
JPN Edition(in Japanese)
D Information & Systems
Trans.Inf.&Syst.
JPN Edition(in Japanese)
Abstracts of JPN Edition
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
Archive
Volume List
Trans.Fundamentals.
Trans.Commun.
Trans.Electron.
Trans.Inf.&Syst.
Transactions (1976-1990)
Volume List [JPN Edition]
A JPN Edition(in Japanese)
B JPN Edition(in Japanese)
C JPN Edition(in Japanese)
D JPN Edition(in Japanese)
Editorial Board & Reviewers
Open Access Papers
Trans. Commun.
Trans. Commun.(JPN Edition)
Link
Subscription
Join IEICE
Library/Nonmember
Pay Per View
A Fundamentals
B Communications
C Electronics
D Information & Systems
For Authors
IEICE Home Page
Citation Index
Privacy Policy
Copyright & Permissions
Copyright (c) by IEICE
Keyword : brute-force algorithm
A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection
Seongyong AHN
Hyejeong HONG
HyunJin KIM
Jin-Ho AHN
Dongmyong BAEK
Sungho KANG
Publication:
IEICE TRANSACTIONS on Communications
Publication Date:
2010/09/01
Vol.
E93-B
No.
9
pp.
2440-2442
Type of Manuscript:
LETTER
Category:
Network Management/Operation
Keyword:
network intrusion detection system
,
deep packet inspection
,
pattern matching
,
brute-force algorithm
,
Summary
|
Full Text:PDF
(122.7KB)