IEICE SEARCH SYSTEM

Keyword : bridging fault

Layout-Based Detection Technique of Line Pairs with Bridging Fault Using I_DDQ Masaru SANADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2004/03/01 Vol. E87-D No. 3 pp. 557-563 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSI) Category: Fault Detection Keyword: I_DDQ, bridging fault, logic, layout structure, fault diagnosis,
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IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates Masaki HASHIZUME Teppei TAKEDA Masahiro ICHIMIYA Hiroyuki YOTSUYANAGI Yukiya MIURA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1534-1541 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: Current Test Keyword: IDDQ sensor, CMOS, IDDQ test, bridging fault,
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Testable Static CMOS PLA for IDDQ Testing Masaki HASHIZUME Hiroshi HOSHIKA Hiroyuki YOTSUYANAGI Takeomi TAMESADA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/06/01 Vol. E84-A No. 6 pp. 1488-1495 Type of Manuscript: Special Section PAPER (Special Section on Papers Selected from 2000 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2000)) Category: Keyword: static PLA, testable design, IDDQ test, bridging fault,
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Analysis of I_DDQ Occurrence in Testing Arabi KESHK Yukiya MIURA Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2001/04/01 Vol. E84-D No. 4 pp. 534-536 Type of Manuscript: LETTER Category: Computer System Element Keyword: I_DDQ testing, bridging fault, fault analysis,
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An Iterative Improvement Method for Generating Compact Tests for IDDQ Testing of Bridging Faults Tsuyoshi SHINOGI Terumine HAYASHI
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 682-688 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: IDDQ Testing Keyword: compaction, IDDQ testing, iterative improvement method, bridging fault, ATPG,
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Test Generation for Sequential Circuits under IDDQ Testing Toshiyuki MAEDA Yoshinobu HIGAMI Kozo KINOSHITA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1998/07/20 Vol. E81-D No. 7 pp. 689-696 Type of Manuscript: Special Section PAPER (Special Issue on Test and Diagnosis of VLSI) Category: IDDQ Testing Keyword: sequential circuit, test generation, IDDQ testing, bridging fault,
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A Single Bridging Fault Location Technique for CMOS Combinational Circuits Koji YAMAZAKI Teruhiko YAMADA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 1995/07/20 Vol. E78-D No. 7 pp. 817-821 Type of Manuscript: Special Section PAPER (Special Issue on Verification, Test and Diagnosis of VLSI Systems) Category: Keyword: fault diagnosis, bridging fault, CMOS, combinational circuit,
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