Keyword : behavioral synthesis


Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing
Hiroaki KONOURA Dawood ALNAJJAR Yukio MITSUYAMA Hajime SHIMADA Kazutoshi KOBAYASHI Hiroyuki KANBARA Hiroyuki OCHI Takashi IMAGAWA Kazutoshi WAKABAYASHI Masanori HASHIMOTO Takao ONOYE Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2518-2529
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
reconfigurable architecturesoft errorradiation testbehavioral synthesisstate machine
 Summary | Full Text:PDF(3.8MB)

Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data Implementation
Naohiro HAMADA Hiroshi SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2012/04/01
Vol. E95-C  No. 4 ; pp. 506-515
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design – Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
asynchronous circuitsbehavioral synthesisfloorplanning
 Summary | Full Text:PDF(995KB)

Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism
Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/02/01
Vol. E93-A  No. 2 ; pp. 488-499
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
behavioral synthesisfunction-level partitioninginteger programming problem
 Summary | Full Text:PDF(550.1KB)

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation
Junbo YU Qiang ZHOU Gang QU Jinian BIAN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3151-3159
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
peak temperaturerebindingreallocationbehavioral synthesis
 Summary | Full Text:PDF(1MB)

Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2009/05/01
Vol. E92-D  No. 5 ; pp. 972-984
Type of Manuscript:  Special Section PAPER (Special Section on Formal Approach)
Category: Hardware Verification
Keyword: 
high-level synthesisbehavioral synthesisformal verificationequivalence checking
 Summary | Full Text:PDF(1022KB)

Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis
Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA Katsuya ISHII 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2853-2862
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
behavioral synthesisfunction-level partitioninginteger programming problem
 Summary | Full Text:PDF(347.1KB)

Function Call Optimization for Efficient Behavioral Synthesis
Yuko HARA Hiroyuki TOMIYAMA Shinya HONDA Hiroaki TAKADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/09/01
Vol. E90-A  No. 9 ; pp. 2032-2036
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
behavioral synthesisfunction callsinteger programming problem
 Summary | Full Text:PDF(138.1KB)

Unified Representation for Speculative Scheduling: Generalized Condition Vector
Kazutoshi WAKABAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3408-3415
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
behavioral synthesisC-based design control-intensive circuitscondition vectorspeculationcode-motiontransformation
 Summary | Full Text:PDF(759.8KB)

Study and Analysis of System LSI Design Methodologies Using C-Based Behavioral Synthesis
Hidefumi KUROKAWA Hiroyuki IKEGAMI Motohide OTSUBO Kiyoshi ASAO Kazuhisa KIRIGAYA Katsuya MISU Satoshi TAKAHASHI Tetsuji KAWATSU Kouji NITTA Hiroshi RYU Kazutoshi WAKABAYASHI Minoru TOMOBE Wataru TAKAHASHI Akira MUKOUYAMA Takashi TAKENAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A  No. 4 ; pp. 787-798
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
C-based designbehavioral synthesisverificationdesign productivitymodel abstraction
 Summary | Full Text:PDF(2.1MB)

Hardware Algorithm Optimization Using Bach C
Kazuhisa OKADA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/04/01
Vol. E85-A  No. 4 ; pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 14th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
high level synthesisbehavioral synthesisC languageBach C
 Summary | Full Text:PDF(341.7KB)

CAM Processor Synthesis Based on Behavioral Descriptions
Nozomu TOGAWA Tatsuhiko WAKUI Tatsuhiko YODEN Makoto TERAJIMA Masao YANAGISAWA Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2464-2473
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design and High-level Synthesis
Keyword: 
content addressable memoryfunctional memorybehavioral synthesisbehavioral descriptionhigh-level synthesis
 Summary | Full Text:PDF(699.5KB)

Thread Composition Method for Hardware Compiler Bach Maximizing Resource Sharing among Processes
Mizuki TAKAHASHI Nagisa ISHIURA Akihisa YAMADA Takashi KAMBE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2456-2463
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Co-design and High-level Synthesis
Keyword: 
behavioral partitioningthread compositionbehavioral synthesis
 Summary | Full Text:PDF(671.1KB)

Combining Architectural Simulation and Behavioral Synthesis
Abderrazak JEMAI Polen KISSION Ahmed Amine JERRAYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1756-1766
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
architectural simulationbehavioral synthesisVHDL
 Summary | Full Text:PDF(887.4KB)