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Keyword : at-speed testing

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors Masato NAKAZATO Michiko INOUE Satoshi OHTAKE Hideo FUJIWARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2008/03/01 Vol. E91-D No. 3 pp. 763-770 Type of Manuscript: Special Section PAPER (Special Section on Test and Verification of VLSIs) Category: High-Level Testing Keyword: software-based self-test, processor, test program template, design for testability, error masking, at-speed testing,
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Channel-Count-Independent BIST for Multi-Channel SerDes Kouichi YAMAGUCHI Muneo FUKAISHI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2006/03/01 Vol. E89-C No. 3 pp. 314-319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era) Category: Interface and Interconnect Techniques Keyword: SerDes, BIST, at-speed testing, PRBS, multi-channel synchronization,
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Hybrid BIST Design for n-Detection Test Using Partially Rotational Scan Kenichi ICHINO Takeshi ASAKAWA Satoshi FUKUMOTO Kazuhiko IWASAKI Seiji KAJIHARA
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2002/10/01 Vol. E85-D No. 10 pp. 1490-1497 Type of Manuscript: Special Section PAPER (Special Issue on Test and Verification of VLSI) Category: BIST Keyword: hybrid BIST, unmodeled fault, n-detection test, partially rotational scan, at-speed testing,
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