Keyword : array partitioning


Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis
Akihiro SUDA Hideki TAKASE Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2498-2506
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
high-level synthesisarray partitioningbuffer managementPolyhedral Optimization
 Summary | Full Text:PDF(1.2MB)