Keyword : area-efficient


A Low-Cost VLSI Architecture of Multiple-Size IDCT for H.265/HEVC
Heming SUN Dajiang ZHOU Peilin LIU Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A  No. 12 ; pp. 2467-2476
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
HEVCIDCTSRAMarea-efficientvideo coding
 Summary | Full Text:PDF(3.1MB)

An Area-Efficient, Low-Power CMOS Fractional Bandgap Reference
Indika U. K. BOGODA APPUHAMYLAGE Shunsuke OKURA Toru IDO Kenji TANIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/06/01
Vol. E94-C  No. 6 ; pp. 960-967
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
bandgap reference (BGR)area-efficientlow-powertemperature coefficientCMOS
 Summary | Full Text:PDF(777.6KB)

A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits
Hiroaki YAMAOKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/06/01
Vol. E87-C  No. 6 ; pp. 1069-1077
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLAhigh-speedarea-efficientdual-rail
 Summary | Full Text:PDF(1.5MB)

A Logic-Cell-Embedded PLA (LCPLA): An Area-Efficient Dual-Rail Array Logic Architecture
Hiroaki YAMAOKA Hiroaki YOSHIDA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/02/01
Vol. E87-C  No. 2 ; pp. 238-245
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
PLAlogic celldual-railarray logicarea-efficient
 Summary | Full Text:PDF(585.8KB)