Keyword : adder


Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs
Ken HAYAMIZU Nozomu TOGAWA Masao YANAGISAWA Youhua SHI 
Publication:   
Publication Date: 2018/07/01
Vol. E101-A  No. 7 ; pp. 1014-1024
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
approximate computingenergy-efficientadderGeAr
 Summary | Full Text:PDF(2.7MB)

Low Power Design of Asynchronous Datapath for LDPC Decoder
XiaoBo JIANG DeSheng YE HongYuan LI WenTao WU XiangMin XU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/09/01
Vol. E96-A  No. 9 ; pp. 1857-1863
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
LDPC codeasynchronous designlow poweraddercomparatorcomparator-MUX
 Summary | Full Text:PDF(2.2MB)

High Throughput Parallel Arithmetic Circuits for Fast Fourier Transform
Ryosuke NAKAMOTO Sakae SAKURABA Alexandre MARTINS Takeshi ONOMI Shigeo SATO Koji NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 280-287
Type of Manuscript:  Special Section PAPER (Special Section on Superconducting Signal Processing Technologies)
Category: 
Keyword: 
SFQsuper-conductive circuitsFFTmultiplieradder
 Summary | Full Text:PDF(2MB)

100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process
Yuki YAMANASHI Toshiki KAINUMA Nobuyuki YOSHIKAWA Irina KATAEVA Hiroyuki AKAIKE Akira FUJIMAKI Masamitsu TANAKA Naofumi TAKAGI Shuichi NAGASAWA Mutsuo HIDAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/04/01
Vol. E93-C  No. 4 ; pp. 440-444
Type of Manuscript:  Special Section PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: Digital Applications
Keyword: 
single flux quantum circuitJosephson junctioncell libraryadder
 Summary | Full Text:PDF(668.8KB)

Comparisons of Synchronous-Clocking SFQ Adders
Naofumi TAKAGI Masamitsu TANAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/04/01
Vol. E93-C  No. 4 ; pp. 429-434
Type of Manuscript:  INVITED PAPER (Special Section on Frontiers of Superconductive Electronics)
Category: 
Keyword: 
single-flux-quantum (SFQ) circuitadderhardware algorithm
 Summary | Full Text:PDF(274.2KB)

Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders
Debatosh DEBNATH Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1492-1500
Type of Manuscript:  Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword: 
three-level networklogic minimizationadderprogrammable logic
 Summary | Full Text:PDF(724.5KB)

A Sub-1 V Bootstrap Pass-Transistor Logic
Koji FUJII Takakuni DOUSEKI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/04/01
Vol. E86-C  No. 4 ; pp. 604-611
Type of Manuscript:  Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
Category: Circuit Design
Keyword: 
pass-transistor logicbootstraplow voltageadder
 Summary | Full Text:PDF(691.4KB)

A New Algorithm for the Configuration of Fast Adder Trees
Alberto PALACIOS-PAWLOVSKY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2426-2430
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
multiplieradderWallace treepartial product additionDadda tree
 Summary | Full Text:PDF(10.7MB)

Representations of Multiple-Output Functions Using Binary Decision Diagrams for Characteristic Functions
Hafiz Md. HASAN BABU Tsutomu SASAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/11/25
Vol. E82-A  No. 11 ; pp. 2398-2406
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
binary decision diagram (BDD)characteristic function (CF)multiple-output functionvariable orderinglogic simulationadderbit-counting functionmultiplier
 Summary | Full Text:PDF(563.6KB)

Design Considerations of Data-Driven Self-Timed RSFQ Adder Circuits
Nobuyuki YOSHIKAWA Hiroshi TAGO Kaoru YONEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/10/25
Vol. E81-C  No. 10 ; pp. 1618-1626
Type of Manuscript:  INVITED PAPER (Special Issue on Low- and High-Temperature Superconductive Electron Devices and Their Applications)
Category: Digital Applications
Keyword: 
RSFQ logic circuitssingle flux quantumsuperconducting circuitshigh-speed integrated circuitsadder
 Summary | Full Text:PDF(708.1KB)

Single-Electron Logic Systems Based on the Binary Decision Diagram
Noboru ASAHI Masamichi AKAZAWA Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Vol. E81-C  No. 1 ; pp. 49-56
Type of Manuscript:  Special Section PAPER (Special Issue on Technology Challenges for Single Electron Devices)
Category: 
Keyword: 
binary decision diagramBDDsingle electronlogic circuitaddercomparator
 Summary | Full Text:PDF(613.4KB)

A Synchronous Completion Prediction Adder (SCPA)
Jeehan LEE Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 606-609
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
adderCLAcompletion predictioncompletion detection
 Summary | Full Text:PDF(228KB)

Analysis of the Delay Distributions of 0.5 µm SOI LSIs
Toshiaki IWAMATSU Takashi IPPOSHI Yasuo YAMAGUCHI Kimio UEDA Koichiro MASHIKO Shigeto MAEGAWA Yasuo INOUE Tadashi HIRAO Tdashi NISHIMURA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/03/25
Vol. E80-C  No. 3 ; pp. 464-471
Type of Manuscript:  Special Section PAPER (Special Issue on SOI Devices and Their Process Technologies)
Category: 
Keyword: 
SOISIMOXdivideradderhigh-speedlow voltage
 Summary | Full Text:PDF(735.3KB)