Keyword : VLSI


Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology
Tian WANG Xiaoxin CUI Kai LIAO Nan LIAO Xiaole CUI Dunshan YU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/08/01
Vol. E99-C  No. 8 ; pp. 974-983
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
VLSIFinFETstandard cellstackingback biasing
 Summary | Full Text:PDF(4MB)

Hybrid Message-Passing Algorithm and Architecture for Decoding Cyclic Non-binary LDPC Codes
Yichao LU Gang HE Guifen TIAN Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A  No. 12 ; pp. 2652-2659
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
Belief propagation algorithmiterative majority-logic decodinglow-density parity-check codesnon-binaryVLSI
 Summary | Full Text:PDF(1.6MB)

Development of Cryogenic Readout Electronics for Far-Infrared Astronomical Focal Plane Array
Hirohisa NAGATA Takehiko WADA Hirokazu IKEDA Yasuo ARAI Morifumi OHNO Koichi NAGASE 
Publication:   IEICE TRANSACTIONS on Communications
Publication Date: 2011/11/01
Vol. E94-B  No. 11 ; pp. 2952-2960
Type of Manuscript:  INVITED PAPER (Special Section on Space, Aeronautical and Navigational Technologies in Conjunction with Main Topics of WSANE and ICSANE)
Category: 
Keyword: 
far-infrared astronomycryogenic readout electronicscharge amplifierVLSIFD-SOI-CMOS
 Summary | Full Text:PDF(1.8MB)

A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects
Jongsun KIM Gyungsu BYUN M. Frank CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5 ; pp. 854-857
Type of Manuscript:  BRIEF PAPER
Category: 
Keyword: 
interconnectcommunicationRF interconnectwire line transceiverVLSI
 Summary | Full Text:PDF(638.4KB)

A Novel Low-Cost High-Throughput CAVLC Decoder for H.264/AVC
Kyu-Yeul WANG Byung-Soo KIM Sang-Seol LEE Dong-Sun KIM Duck-Jin CHUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2011/04/01
Vol. E94-D  No. 4 ; pp. 895-904
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
CAVLC decodermulti-symbol decoderVLSIH.264/AVC
 Summary | Full Text:PDF(935.6KB)

A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation
Yoshiki YUNBE Masayuki MIYAMA Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2010/12/01
Vol. E93-D  No. 12 ; pp. 3284-3293
Type of Manuscript:  PAPER
Category: Computer System
Keyword: 
affine motion modelmotion estimationvideo segmentationreal-time processingVLSIFPGA
 Summary | Full Text:PDF(2.1MB)

A High-Throughput Binary Arithmetic Coding Architecture for H.264/AVC CABAC
Yizhong LIU Tian SONG Takashi SHIMAMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/09/01
Vol. E93-A  No. 9 ; pp. 1594-1604
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
H.264/AVC encoderCABACentropy codingbinary arithmetic codingVLSI
 Summary | Full Text:PDF(1.5MB)

Highly Parallel Fractional Motion Estimation Engine for Super Hi-Vision 4k4k@60 fps
Yiqing HUANG Takeshi IKENAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/03/01
Vol. E93-C  No. 3 ; pp. 244-252
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
super hi-visionH.264/AVCFMEVLSI
 Summary | Full Text:PDF(1.1MB)

Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm
Ming-Chih CHEN Shen-Fu HSIAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3221-3228
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword: 
AESVLSIcommon subexpression elimination (CSE)information securitylogic synthesis
 Summary | Full Text:PDF(1009KB)

Adaptive Sub-Sampling Based Reconfigurable SAD Tree Architecture for HDTV Application
Yiqing HUANG Qin LIU Satoshi GOTO Takeshi IKENAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/11/01
Vol. E92-A  No. 11 ; pp. 2819-2829
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Video Coding
Keyword: 
reconfigurable architectureH.264/AVCSAD treeVLSIHDTV
 Summary | Full Text:PDF(1.3MB)

Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model
Yanming JIA Yici CAI Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/12/01
Vol. E91-A  No. 12 ; pp. 3783-3792
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSIbuffer insertionphysical designDFMdummy fill
 Summary | Full Text:PDF(373.2KB)

Implementation of Multi-Agent Object Attention System Based on Biologically Inspired Attractor Selection
Ryoji HASHIMOTO Tomoya MATSUMURA Yoshihiro NOZATO Kenji WATANABE Takao ONOYE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/10/01
Vol. E91-A  No. 10 ; pp. 2909-2917
Type of Manuscript:  Special Section PAPER (Special Section on Smart Multimedia & Communication Systems)
Category: Video Processing Systems
Keyword: 
VLSIobject attentionattractor selectionbiological modelmulti-agent
 Summary | Full Text:PDF(1MB)

A 158 MS/s JPEG 2000 Codec with a Bit-Plane and Pass Parallel Embedded Block Coder for Low Delay Image Transmission
Masayuki MIYAMA Yuusuke INOIE Takafumi KASUGA Ryouichi INADA Masashi NAKAO Yoshio MATSUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/08/01
Vol. E91-A  No. 8 ; pp. 2025-2034
Type of Manuscript:  Special Section PAPER (Special Section on Signal Processing)
Category: 
Keyword: 
JPEG 2000EBCOTVLSIlow delayimage transmission
 Summary | Full Text:PDF(1.5MB)

An Asynchronous Circuit Design Technique for a Flexible 8-Bit Microprocessor
Nobuo KARAKI Takashi NANMOTO Satoshi INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2008/05/01
Vol. E91-C  No. 5 ; pp. 721-730
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
asynchronous circuit designVerilog+flexible microelectronicsLTPS TFTSUFTLA®VLSIself-heatingdeviation in switching delayQDI4-phase handshaking
 Summary | Full Text:PDF(1.7MB)

A Multiprocessor SoC Architecture with Efficient Communication Infrastructure and Advanced Compiler Support for Easy Application Development
Mohammad ZALFANY URFIANTO Tsuyoshi ISSHIKI Arif ULLAH KHAN Dongju LI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1185-1196
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
multiprocessor-on-a-chipsystem-on-chipscrossbar interconnectVLSI
 Summary | Full Text:PDF(1.3MB)

High-Efficiency VLSI Architecture Design for Motion-Estimation in H.264/AVC
Chun-Lung HSU Mean-Hom HO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2818-2825
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
VLSImotion estimationVBSDH.264/AVC
 Summary | Full Text:PDF(3MB)

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information
Chung-chi LIN Ming-hwa SHEU Huann-keng CHIANG Chih-Jen WEI Chishyan LIAW 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/11/01
Vol. E90-A  No. 11 ; pp. 2575-2583
Type of Manuscript:  PAPER
Category: Image
Keyword: 
de-interlacingprogressive scanscene changeVLSI
 Summary | Full Text:PDF(1.8MB)

Adaptive Low-Error Fixed-Width Booth Multipliers
Min-An SONG Lan-Da VAN Sy-Yen KUO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/06/01
Vol. E90-A  No. 6 ; pp. 1180-1187
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
digital signal processingfixed-width Booth multiplierVLSI
 Summary | Full Text:PDF(953.8KB)

A Block-Based Architecture for Lifting Scheme Discrete Wavelet Transform
Chung-Hsien YANG Jia-Ching WANG Jhing-Fa WANG Chi-Wei CHANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/05/01
Vol. E90-A  No. 5 ; pp. 1062-1071
Type of Manuscript:  PAPER
Category: Image
Keyword: 
discrete wavelet transformJPEG2000lifting schemeline-based DWTVLSI
 Summary | Full Text:PDF(1.9MB)

Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation
Ming SHAO Zhenyu LIU Satoshi GOTO Takeshi IKENAGA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 756-763
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
H.264/AVCFMEcomputation reusinglosslessVLSI
 Summary | Full Text:PDF(780.5KB)

A Hardware Algorithm for Integer Division Using the SD2 Representation
Naofumi TAKAGI Shunsuke KADOWAKI Kazuyoshi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/10/01
Vol. E89-A  No. 10 ; pp. 2874-2881
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticdivisioninteger divisionhardware algorithmsigned-digit representationVLSI
 Summary | Full Text:PDF(377.5KB)

Design Philosophy of a Networking-Oriented Data-Driven Processor: CUE
Hiroaki NISHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/03/01
Vol. E89-C  No. 3 ; pp. 221-229
Type of Manuscript:  INVITED PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
Category: 
Keyword: 
data-drivenmultiprocessingreal-timeVLSI
 Summary | Full Text:PDF(1021.9KB)

Low-Hardware-Cost Motion Estimation with Large Search Range for VLSI Multimedia Processors
Seongsoo LEE Min-Cheol HONG Jae-Kyung WEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/09/01
Vol. E88-D  No. 9 ; pp. 2177-2182
Type of Manuscript:  PAPER
Category: Image Processing and Video Processing
Keyword: 
motion estimationblock matchinglow hardware costoutlier exclusionVLSI
 Summary | Full Text:PDF(639.8KB)

Crosstalk and Congestion Driven Layer Assignment Algorithm
Bin LIU Yici CAI Qiang ZHOU Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/06/01
Vol. E88-A  No. 6 ; pp. 1565-1572
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
congestioncrosstalklayer assignmentVLSI
 Summary | Full Text:PDF(235.4KB)

Power Optimization of an 8051-Compliant IP Microcontroller
Luca FANUCCI Sergio SAPONARA Alexander MORELLO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2005/04/01
Vol. E88-C  No. 4 ; pp. 597-600
Type of Manuscript:  Special Section LETTER (Special Section on Low-Power LSI and Low-Power IP)
Category: 
Keyword: 
low-powerVLSIintellectual property (IP) cells8051 microcontroller
 Summary | Full Text:PDF(184.8KB)

An IP Synthesizer for Limited-Resource DWT Processor
Lan-Rong DUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3047-3056
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
discrete wavelet transformVLSIsilicon intelligent propertyDSPcomputer architecture
 Summary | Full Text:PDF(1.7MB)

An Efficient VLSI Architecture of 1-D Lifting Discrete Wavelet Transform
Pei-Yin CHEN Shung-Chih CHEN 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 2009-2014
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
VLSIdiscrete wavelet transformlifting scheme
 Summary | Full Text:PDF(2.4MB)

Rough Information Processing--A Computing Paradigm for Analog Systems--
Junichi AKITA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1777-1779
Type of Manuscript:  Special Section LETTER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
VLSIanalog circuitinformation processingvision chip
 Summary | Full Text:PDF(199.5KB)

ODiN: A 32-Bit High Performance VLIW DSP for Software Defined Radio Applications
Seung Eun LEE Yong Mu JEONG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1780-1786
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
DSP (Digital Signal Processor)SDR (Software Defined Radio)VLIWVLSI
 Summary | Full Text:PDF(963.4KB)

Perspectives of Low-Power VLSI's
Takayasu SAKURAI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 429-436
Type of Manuscript:  INVITED PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
digitalmemoryapplicationlow powerVLSIleakage
 Summary | Full Text:PDF(1.7MB)

VLSI-Oriented Motion Estimation Using a Steepest Descent Method in Mobile Video Coding
Masayuki MIYAMA Junichi MIYAKOSHI Kousuke IMAMURA Hideo HASHIMOTO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 466-474
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
MPEGmotion estimationgradient based methodsteepest descent methodlow powerVLSI
 Summary | Full Text:PDF(731.6KB)

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Kazutoshi KOBAYASHI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2004/03/01
Vol. E87-D  No. 3 ; pp. 630-636
Type of Manuscript:  Special Section PAPER (Special Section on Test and Verification of VLSI)
Category: Verification
Keyword: 
simulationtestVLSItesterverification
 Summary | Full Text:PDF(1.4MB)

A Fast Sorting VLSI Architecture for General-Purpose Standard Median Filters
Hyeongseok YU Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 698-700
Type of Manuscript:  Special Section LETTER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Image Processing
Keyword: 
VLSIsortingmedian filter
 Summary | Full Text:PDF(481.6KB)

Fast and Low Power Viterbi Search Engine Using Inverse Hidden Markov Model
Bo-Sung KIM Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 695-697
Type of Manuscript:  Special Section LETTER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
VLSIHMMViterbi searchlow-power
 Summary | Full Text:PDF(369.9KB)

A Folded VLSI Architecture of Decision Feedback Equalizer for QAM Modem
Hyeongseok YU Byung Wook KIM Jun-Dong CHO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/03/01
Vol. E87-A  No. 3 ; pp. 628-639
Type of Manuscript:  Special Section PAPER (Special Section on Applications and Implementations of Digital Signal Processing)
Category: Communication Theory and Systems
Keyword: 
decision feedback equalizerQAMVLSIFIR filterfolding
 Summary | Full Text:PDF(3.2MB)

VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform
Pei-Yin CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/01/01
Vol. E87-A  No. 1 ; pp. 275-279
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSIdiscrete wavelet transformlifting scheme
 Summary | Full Text:PDF(1.5MB)

Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms
Jun SAKIYAMA Naofumi HOMMA Takafumi AOKI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3009-3019
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: IP Design
Keyword: 
computer arithmetic algorithmsparallel countersmultipliersdatapathVLSIcircuit synthesis
 Summary | Full Text:PDF(905.4KB)

Novel Built-In Current Sensor for On-Line Current Testing
Chul Ho KWAK Jeong Beom KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/09/01
Vol. E86-C  No. 9 ; pp. 1898-1902
Type of Manuscript:  LETTER
Category: Integrated Electronics
Keyword: 
built-in current sensorcurrent testingVLSIreliability
 Summary | Full Text:PDF(985.6KB)

Carry Propagation Free Adder/Subtracter Using Adiabatic Dynamic CMOS Logic Circuit Technology
Yasuhiro TAKAHASHI Kei-ichi KONTA Kazukiyo TAKAHASHI Michio YOKOYAMA Kazuhiro SHOUNO Mitsuru MIZUNUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/06/01
Vol. E86-A  No. 6 ; pp. 1437-1444
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 2002 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2002))
Category: 
Keyword: 
adiabatic dynamic CMOS logic (ADCL)carry propagation freeadder/subtracterVLSIredundant binary
 Summary | Full Text:PDF(557.9KB)

Low-Power Architecture of a Digital Matched Filter for Direct-Sequence Spread-Spectrum Systems
Takashi YAMADA Shoji GOTO Norihisa TAKAYAMA Yoshifumi MATSUSHITA Yasoo HARADA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2003/01/01
Vol. E86-C  No. 1 ; pp. 79-88
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
matched filterspread-spectrumWCDMAVLSIlow power
 Summary | Full Text:PDF(987.9KB)

A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication
Noriyuki MINEGISHI Ken-ichi ASANO Hirokazu SUZUKI Keisuke OKADA Takashi KAN 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/10/01
Vol. E85-D  No. 10 ; pp. 1571-1578
Type of Manuscript:  Special Section PAPER (Special Issue on Test and Verification of VLSI)
Category: Debugging Multiple Processors
Keyword: 
VLSIdebug methodologyheterogeneous multiple processorIEEE 1149.1reducing debug period
 Summary | Full Text:PDF(1.7MB)

VLSI Architecture and Implementation for Speech Recognizer Based on Discriminative Bayesian Neural Network
Jhing-Fa WANG Jia-Ching WANG An-Nan SUEN Chung-Hsien WU Fan-Min LI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/08/01
Vol. E85-A  No. 8 ; pp. 1861-1869
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: Implementations of Signal Processing Systems
Keyword: 
discriminative Bayesian neural networkspeech recognitionVLSI
 Summary | Full Text:PDF(835.6KB)

A Low-Complexity and High-Resolution Algorithm for the Magnitude Approximation of Complex Numbers
Luca FANUCCI Massimo ROVINI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/07/01
Vol. E85-A  No. 7 ; pp. 1766-1769
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
complex numbermagnitude approximationpower estimationhardware implementationVLSI
 Summary | Full Text:PDF(377.8KB)

An Embedded Zerotree Wavelet Video Coding Algorithm with Reduced Memory Bandwidth
Roberto Y. OMAKI Gen FUJITA Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/03/01
Vol. E85-A  No. 3 ; pp. 703-713
Type of Manuscript:  PAPER
Category: Image
Keyword: 
discrete wavelet transformEmbedded Zerotree Waveletvideo compressionVLSI
 Summary | Full Text:PDF(3.1MB)

Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model
Tadashi SHIBATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/03/01
Vol. E85-A  No. 3 ; pp. 600-609
Type of Manuscript:  INVITED PAPER (Special Section on the Trend of Digital Signal Processing and Its Future Direction)
Category: LSI/Signal Processors
Keyword: 
VLSIneuron MOSfloating-gate MOSimage recognitionvector quantizationpsychological brain model
 Summary | Full Text:PDF(3.4MB)

A Fast Finite Field Multiplier Architecture for High-Security Elliptic Curve Cryptosystems
Sangook MOON Yong Joo LEE Jae Min PARK Byung In MOON Yong Surk LEE 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2002/02/01
Vol. E85-D  No. 2 ; pp. 418-420
Type of Manuscript:  LETTER
Category: Applications of Information Security Techniques
Keyword: 
finite field multiplierelliptic curve cryptographysecurityVLSI
 Summary | Full Text:PDF(185KB)

Design of High-Radix VLSI Dividers without Quotient Selection Tables
Takafumi AOKI Kimihiko NAKAZAWA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2623-2631
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design
Keyword: 
computer arithmeticSRT divisionhigh-radix divisionsigned-digit number systemsVLSI
 Summary | Full Text:PDF(1.2MB)

A Digit-Recurrence Algorithm for Cube Rooting
Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/05/01
Vol. E84-A  No. 5 ; pp. 1309-1314
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
computer arithmeticcube rootinghardware algorithmdigit-recurrence algorithmVLSI
 Summary | Full Text:PDF(255.2KB)

A Low Power Media Processor Core Performable CIF30 fr/s MPEG4/H26x Video Codec
Hideo OHIRA Toshihisa KAMEMARU Hirokazu SUZUKI Ken-ichi ASANO Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 157-165
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLSImedia processor corevideo codinglow powerhigh performance
 Summary | Full Text:PDF(521.6KB)

A Low-Power High-Performance Vector-Pipeline DSP for Low-Rate Videophones
Kazutoshi KOBAYASHI Makoto EGUCHI Takuya IWAHASHI Takehide SHIBAYAMA Xiang LI Kosuke TAKAI Hidetoshi ONODERA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/02/01
Vol. E84-C  No. 2 ; pp. 193-201
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
Category: 
Keyword: 
VLSIDSPMSHVQvideophonevideo compression
 Summary | Full Text:PDF(1001.1KB)

Architecture and Performance Evaluation of a New Functional Memory: Functional Memory for Addition
Kazutoshi KOBAYASHI Masanao YAMAOKA Yukifumi KOBAYASHI Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2400-2408
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword: 
VLSIfunctional memoryDRAMparallel processorblock matching
 Summary | Full Text:PDF(868.6KB)

Radix-2-4-8 CORDIC for Fast Vector Rotation
Takafumi AOKI Ichiro KITAORI Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/06/25
Vol. E83-A  No. 6 ; pp. 1106-1114
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1999 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'99))
Category: 
Keyword: 
computer arithmeticarithmetic circuitsCORDICVLSIdigital signal processing
 Summary | Full Text:PDF(1.2MB)

Simplified Block Matching Criteria for Motion Estimation
Jar-Ferr YANG Shu-Sheng HAO Wei-Yuan LU 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2000/04/25
Vol. E83-D  No. 4 ; pp. 922-930
Type of Manuscript:  PAPER
Category: Image Processing, Image Pattern Recognition
Keyword: 
block matchingVLSIXORPDCMADmotion estimation
 Summary | Full Text:PDF(2.3MB)

VLSI Architecture of Switching Control for AAL Type2 Switch
Masahide HATANAKA Toshihiro MASAKI Takao ONOYE Koso MURAKAMI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/03/25
Vol. E83-A  No. 3 ; pp. 435-441
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
ATMAAL type2AAL2 switchVLSI
 Summary | Full Text:PDF(1.2MB)

A Bit-Operation Algorithm of the Median-Cut Quantization and Its Hardware Architecture
Shogo MURAMATSU Hitoshi KIYA Akihiko YAMADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/02/25
Vol. E83-A  No. 2 ; pp. 320-328
Type of Manuscript:  Special Section PAPER (Special Section on Intelligent Signal and Image Processing)
Category: 
Keyword: 
adaptive quantizationmedian valuemotion estimationVLSI
 Summary | Full Text:PDF(1.1MB)

A Hierarchical Circuit Clustering Algorithm with Stable Performance
Seung-June KYOUNG Kwang-Su SEONG In-Cheol PARK Chong-Min KYUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/09/25
Vol. E82-A  No. 9 ; pp. 1987-1993
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
VLSICADpartitioningclustering
 Summary | Full Text:PDF(417.3KB)

Equipment Simulation of Production Reactors for Silicon Device Fabrication
Christoph WERNER 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1999/06/25
Vol. E82-C  No. 6 ; pp. 992-996
Type of Manuscript:  INVITED PAPER (Special Issue on TCAD for Semiconductor Industries)
Category: 
Keyword: 
equipment simulationCVD reactorchemical vapor depositionTCADcomputer modelingcomputational fluid dynamicssilicon devicesVLSI
 Summary | Full Text:PDF(3.1MB)

SCR : SPICE Netlist Reduction Tool
Mototaka KURIBAYASHI Masaaki YAMADA Hideki TAKEUCHI Masami MURAKATA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/03/25
Vol. E82-A  No. 3 ; pp. 417-423
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 11th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
SPICEreductiontransistorsimulationCADVLSI
 Summary | Full Text:PDF(442.9KB)

A New Routing Method Considering Neighboring-Wire Capacitance Constraints
Takumi WATANABE Kimihiro YAMAKOSHI Hitoshi KITAZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2679-2687
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routingwire capacitancedeep-submicron designCADVLSI
 Summary | Full Text:PDF(839.1KB)

A New Processor Architecture for Digital Signal Transport Systems
Minoru INAMORI Kenji ISHII Akihiro TSUTSUI Kazuhiro SHIRAKAWA Toshiaki MIYAZAKI Hiroshi NAKADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1408-1415
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
processorVLSIprotocol processingarchitecture
 Summary | Full Text:PDF(772.5KB)

A Low-Power DSP Core Architecture for Low Bitrate Speech Codec
Hiroyuki OKUHATA Morgan H. MIKI Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/08/25
Vol. E81-A  No. 8 ; pp. 1616-1621
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
G. 723. 1VLSIDSPlow-powerspeech codec
 Summary | Full Text:PDF(664.7KB)

Dedicated Design of Motion Estimator with Bits Truncation Fast Algorithm
Li JIANG Dongju LI Shintaro HABA Chawalit HONSAWEK Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/08/25
Vol. E81-A  No. 8 ; pp. 1667-1675
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
MPEGHDTVVLSIMSPAbits truncationmotion estimation
 Summary | Full Text:PDF(943.4KB)

Unified Tag Memory Architecture with Snoop Support
Yonghwan LEE Wookyeong JEONG Yongsurk LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1172-1175
Type of Manuscript:  Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Systems and Control
Keyword: 
unified tagcache tagTLBVLSI
 Summary | Full Text:PDF(362.6KB)

Polling-Based Real-Time Software for MPEG2 System Protocol LSIs
Jiro NAGANUMA Makoto ENDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 695-701
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
MPEG2protocol processingmultiplexer/demultiplexerreal-time softwareembedded systemHW/SW co-designVLSI
 Summary | Full Text:PDF(648.1KB)

A VLSI Architecture for Motion Estimation Core Dedicated to H. 263 Video Coding
Gen FUJITA Takao ONOYE Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/05/25
Vol. E81-C  No. 5 ; pp. 702-707
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Network, and DRAM LSIs)
Category: 
Keyword: 
H. 263VLSImotion estimationhierarchical search
 Summary | Full Text:PDF(604KB)

An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
Takumi WATANABE Yusuke OHTOMO Kimihiro YAMAKOSHI Yuichiro TAKEI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 677-684
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
routing methodologymaze routerlayoutCADVLSI
 Summary | Full Text:PDF(835KB)

A Fast Minimum Cost Flow Algorithm for Regenerating Optimal Layout of Functional Cells
Itthichai ARUNGSRISANGCHAI Yuji SHIGEHIRO Isao SHIRAKAWA Hiromitsu TAKAHASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/12/25
Vol. E80-A  No. 12 ; pp. 2589-2599
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
VLSIfabrication technologymask patternLPflow
 Summary | Full Text:PDF(870.3KB)

An Efficient Method for The Derivation of Signal Flow Direction in Digital CMOS VLSI
Ahmed Riadh BABA-ALI Ahcene FARAH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1902-1907
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSICADMOSswitch-levelsignal flow
 Summary | Full Text:PDF(537.4KB)

Statistical Estimation of CMOS Circuit Activity under Probabilistic Delays
Tan-Li CHOU Kaushik ROY 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1915-1923
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSIstatistical power estimation
 Summary | Full Text:PDF(742.4KB)

An Asynchronous Cell Library for Self-Timed System Designs
Yuk-Wah PANG Wing-yun SIT Chiu-sing CHOY Cheong-fat CHAN Wai-kuen CHAM 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 1997/03/25
Vol. E80-D  No. 3 ; pp. 296-307
Type of Manuscript:  Special Section PAPER (Special Issue on Asynchronous Circuit and System Design)
Category: Design
Keyword: 
self-timed logicasynchronous designstandard cellVLSI
 Summary | Full Text:PDF(1008KB)

A New Rip-Up and Reroute Algorithm for Very Large Scale Gate Arrays
Hiroshi SHIROTA Satoshi SHIBATANI Masayuki TERAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A  No. 3 ; pp. 506-513
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
multilayer routinglayoutCADVLSI
 Summary | Full Text:PDF(748.2KB)

Optimization of the Numbers of Machines and Operators Required for LSI Production
Kazuyuki SAITO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/08/25
Vol. E79-C  No. 8 ; pp. 1112-1119
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
integrated electronicsVLSImanufacturing systemfacility designqueueing model
 Summary | Full Text:PDF(586.6KB)

Systolic Realization of Cyclic Wavelet Transforms and Cyclic Wavelet Packet Transforms
J. W. WANG C. H. CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/08/25
Vol. E79-A  No. 8 ; pp. 1240-1242
Type of Manuscript:  Special Section LETTER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
cyclic wavelet transformscyclic wavelet packet transformsVLSI
 Summary | Full Text:PDF(202.7KB)

Single Chip Implementation of Motion Estimator Dedicated to MPEG2 MP´╝áHL
Takao ONOYE Gen FUJITA Masamichi TAKATSU Isao SHIRAKAWA Nariyoshi YAMAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/08/25
Vol. E79-A  No. 8 ; pp. 1210-1216
Type of Manuscript:  Special Section PAPER (Special Section on Digital Signal Processing)
Category: 
Keyword: 
MPEG2HDTVVLSImotion estimation
 Summary | Full Text:PDF(679.8KB)

A 2.6-ns 64-b Fast and Small CMOS Adder
Hiroyuki MORINAKA Hiroshi MAKINO Yasunobu NAKASE Hiroaki SUZUKI Koichiro MASHIKO Tadashi SUMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/04/25
Vol. E79-C  No. 4 ; pp. 530-537
Type of Manuscript:  Special Section PAPER (Special Issue on Ultra-High-Speed LSIs)
Category: 
Keyword: 
additioncarry look-ahead adderbinary look-ahead addercarry selectmodified carry selectCMOSVLSI
 Summary | Full Text:PDF(642.3KB)

Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures
Takao ONOYE Toshihiro MASAKI Yasuo MORIMOTO Yoh SATO Isao SHIRAKAWA Kenji MATSUMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/03/25
Vol. E79-A  No. 3 ; pp. 330-338
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
Category: 
Keyword: 
MPEG2HDTVVLSIdecorder ASIC
 Summary | Full Text:PDF(823.5KB)

A Hybrid Hierarchical Global Router for Multi-Layer VLSI's
Masayuki HAYASHI Shuji TSUKIYAMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/03/25
Vol. E78-A  No. 3 ; pp. 337-344
Type of Manuscript:  Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
Category: VLSI Design Technology and CAD
Keyword: 
hybrid hierarchical routerglobal routingmulti-layer routingCADVLSI
 Summary | Full Text:PDF(709.6KB)

VLSI Implemented 60 Mb/s QPSK/OQPSK Burst Digital Demodulator for Radio Application
Yoichi MATSUMOTO Kiyoshi KOBAYASHI Tetsu SAKATA Kazuhiko SEKI Shuji KUBOTA Shuzo KATO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1994/12/25
Vol. E77-C  No. 12 ; pp. 1873-1880
Type of Manuscript:  Special Section PAPER (Special Issue on Multimedia, Analog and Processing LSIs)
Category: Multimedia System LSIs
Keyword: 
demodulatorcarrier recoverybit-timing recoveryVLSITDMA
 Summary | Full Text:PDF(794.8KB)

A Hierarchical Global Router for Mscro-Block-Embedded Sea-of-Gates
Mototaka KURIBAYASHI Masaaki YAMADA Takashi MITSUHASHI Nobuyuki GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/10/25
Vol. E76-A  No. 10 ; pp. 1694-1704
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
VLSICADrouterhierarchical decomposition
 Summary | Full Text:PDF(1MB)

Research Topics and Results on Simulation for VLSI
Isao SHIRAKAWA Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/07/25
Vol. E76-A  No. 7 ; pp. 1070-1076
Type of Manuscript:  Special Section PAPER (Special Section on Surveys of Researches in CAS Fields in the Last Two Decades, I)
Category: 
Keyword: 
VLSIcircuit simulationlogic simulation
 Summary | Full Text:PDF(717.3KB)

A Recycling Scheme for Layout Patterns Used in an Old Fabrication Technology
Yuji SHIGEHIRO Isao SHIRAKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/06/25
Vol. E76-A  No. 6 ; pp. 886-893
Type of Manuscript:  Special Section PAPER (Special Section on Papers Selected from 1992 Joint Technical Conference on Circuits/Systems,Computers and Communications (JTC-CSCC'92))
Category: Algorithms for VLSI Design
Keyword: 
VLSIfabrication technologymask patternlayout description
 Summary | Full Text:PDF(707.2KB)

VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations
Shoji KAWAHITO Yasuhiro MITSUI Tetsuro NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 446-454
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
multiple-valued logicmultiple-valued current-mode circuitscarry-propagation-free additionhigh-speed arithmeticVLSI
 Summary | Full Text:PDF(728.2KB)

A High-Speed Special Purpose Processor for Underground Object Detection
Hiroshi MIYANAGA Hironori YAMAUCHI Yuji NAGASHIMA Tsutomu HOSAKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1992/10/25
Vol. E75-C  No. 10 ; pp. 1250-1258
Type of Manuscript:  Special Section PAPER (Special Issue on Microprocessors)
Category: Application Specific Processors
Keyword: 
FFTVLSIunderground objectspulse radar
 Summary | Full Text:PDF(1.1MB)

Timing Driven Placement Based on Fuzzy Theory
Ze Cang GU Shoichiro YAMADA Shojiro YONEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/07/25
Vol. E75-A  No. 7 ; pp. 917-919
Type of Manuscript:  Special Section LETTER (Special Section on the 1992 IEICE Spring Conference)
Category: 
Keyword: 
fuzzytimingplacementVLSI
 Summary | Full Text:PDF(159KB)